查询词典 sequential logic

Since sequential redundancies are difficult to identify, retiming is introduced in the work to convert the sequential redundancies into combinational redundancies which can be easily removed by some mature combinational optimization tools.

针对时序冗余难于识别的问题，这种方法引入重定时技术，将电路中的时序冗余转换为冗余的组合逻辑，然后利用已有的比较成熟的组合逻辑优化工具将其去除。

And a retiming scheme based on the above method is also presented to optimize the timing behavior of sequential circuits. Also from waveform polynomials of sequential circuits, a precise clocking method based on multiple-period sensitization is presented.

为了适应超深亚微米电路测试的要求，本文建立了一种新的基于布尔过程论的逻辑级噪声预测模型，用波形多项式描述的同时发生的跳变数来预测噪声大小，并生成能产生最大跳变数目的输入波形；然后同基于波形敏化的长敏化通路选择法相结合，形成一种能产生最大噪声效应的敏化测试波形生成新方法。

Dr. de Bono calls this vertical thinking, the traditional, sequential, Aristotelian thinking of logic, moving firmly from one step to the next, like toy blocks being built one on top of the other.

德博诺医生把这一模式称为纵向思维——这是一种传统的、连续的、亚里士多德式的逻辑思维，固定地从一步迈向下一步，就像是玩具积木一块搭在另一块上面那样。

To learn the principles of combinational and sequential logic circuits and to be familiar with the basis of digital system. The course will cover the contents of VHDL and the principles of CPLD/FPGA.

本课程之目标在於帮助学生了解数位系统中组合及序向逻辑的原理及设计方法，以建立数位系统设计之基础，并辅以VHDL硬体描述语言的模拟实习以验证理论并熟悉CPLD/FPGA之原理。

This solution is suitable for implementation of various kinds of medium-scale combinatorial and sequential logic circuit.

也给出了数字电路仿真算法设计的具体描述。

This is an electronic book is on a "sequential logic circuit design and special combinations", we hope to help!

这是一本电子书，是关于"时序电路逻辑设计与特殊组合"的，望对大家有所帮助！

It is a sequential logic circuit; its outputs depend not only on the current input values, but also on how they have changed in the past.

这是一种时序电路，它的输出不仅依赖于当前的输入值，还与以前输入值是如何变化的有关。

PLC programming technique includes experience design method, logic design method, cycle diagram design method and sequential control design method.

PLC编程技术包括：经验设计法，逻辑设计法、时序图设计法、顺序控制设计法等编程方法。

On the design of algorithms, a novel exact hierarchical delay analysis method for general circuits is proposed; based on the sensitization theorem for sequential circuits, an exact minimizing clocking method is proposed; based on Boolean process, a waveform simulation method considering interconnecting delay for logic circuit and a parallel waveform simulation method are proposed; a new method that transforms bit-level waveform polynomial to word-level polynomial model is proposed; a multiple valued synthesis algorithm based on multiple valued Boolean process and a wire-centered delay synthesis policy are proposed, in which timing planning, floorplanning, wire planning and optimal clock skew in early design are considered; a two-layers channel routing method for minimizing crosstalk under grid mode is proposed; based on the transition numbers theorems for waveform polynomial, a new method for generation of test with noise effects is proposed.

算法设计方面，提出了一种精确的通用电路层次化延时分析方法；基于时序电路的敏化定理提出时序电路最小时钟周期精确确定方法；提出基于Boolean过程论的考虑互连延迟的逻辑电路波形模拟方法，在分析了波形模拟适合并行化基础上，进一步提出一种并行波形模拟算法；提出一种将位级电路波形多项式描述转化成字级多项式描述的新方法；提出一种基于多值Boolean过程的多值电路综合算法以及一种将前期设计定时规划、前期设计的布局规划和线网结构化方法及低偏移的时钟分配等技术相结合的面向互连延时的综合策略；提出一种串绕最小化的网格模式下的双层通道布线方法；从波形多项式描述跳变数的定理出发提出了一种考虑噪声效应的测试生成新方法。

For example, building direct current sequential logic circuits out of relays requires additional hardware to cope with the problem of contact bounce.

例如，建设直流时序逻辑电路的继电器，需要额外的硬件，以应付的问题，联系反弹。

"Second Life is remarkably easy to work with, and is very popular,"

"第二次生命是显着容易的工作，并且很受欢迎，"

For example, we usually assume that materials are homogeneous and isotropic and free of internal defects or flaws.

为了得到适合有限元分析的模型，我们必须经过如图2所示的简化步骤。