查询词典 logic level

The real-time target track processing system is designed which is constructed by the high performance DSP chipset TMS320C6416 as the core digital processor, the huge reprogrammable logic chipset CPLD as the system logic control and the field reprogrammable array FPGA as the image preprocessing chipset to sampled video digital image.

为了解决算法复杂性及满足工程实时性，设计了以高性能的DSP芯片TMS320C6416为核心处理器，结合大规模可编程逻辑器件CPLD进行逻辑控制以及现场可编程门阵列FPGA对采集的视频数字图像做预处理的实时目标识别跟踪处理平台。

The real2time target t rack processing system is designed which is const ruc2 ted by t he high performance DSP chip set TMS320C6416 as the core digital p rocessor , t he huge rep rogrammable logic chip set CPLD as t he system logic cont rol and the field reprogrammable array FPGA as t he image p reprocessing chip set to sampled video digital image.

为了解决算法复杂性及满足工程实时性，设计了以高性能的DSP 芯片TMS320C6416 为核心处理器，结合大规模可编程逻辑器件 CPLD 进行逻辑控制以及现场可编程门阵列FPGA 对采集的视频数字图像做预处理的实时目标识别跟踪处理平台。

Traditionally,Aristotelian logic,which dominated the logic scene for over 2 00 years(up to the beginning od the twentieth century),dealt almost exclusively with argument made up of sentences like "All A are B" and "some A are B".

按照传统的观点，统治了逻辑学界2000年之久的亚里士多德逻辑(直至20世纪初)，几乎唯一地处理由诸如句子&所有的A是B&以及&一些A是B&所组成的论证。

In the book, Boole set forth the formal axioms of logic (much like the axioms of geometry) on which the field of symbolic logic is built.

在这本书里，向前 Boole 装置逻辑的正式公理在上建立了符号逻辑的领域

Probabilistic logic was proposed by Boole~[42] and rediscovered by Nilsson~[12]There exist some severe problems in Nilssons probabilistic logic, for example, high computational complexity and inferential vacuousness-inferences typically lead to large probability intervals.

Nilsson的概率逻辑存在着一些严峻的问题，例如高计算复杂度，推理的盲目性，比较典型的是，推理导致巨大的概率区间。

The paper firstly examines the philosophical background. It holds that philosophical currents such as phenomenology and existentialism have an effect on this theory to some degree, and then traces the inner logic of origin and development of the theory from post-modernism and "anti-cultural" trend. Afterwards, it generalizes several important post-modern theorists such as Alain Robbe-Grillet, Roland Barthes, Susan Sontag, Michel Foucault, Jacques Derrida, Gilles Deleuze, Jean Baudrillard and so on. The paper proposes that "against-interpretation" is not only a literary critical claim, but also a cultural theory. Its attitude that overthrows and rebells tradition makes it inevitably tend towards the logic of deconstruction.Chapter two, chapter three and chapter four analyze in detail of Robbe-Grillet, sontag and Baudrillard respectively, and systematicly discuss the aesthetics pursuit and the cultural significance of the theory against interpretation through comparing the thoughts of them.

论文首先对反阐释理论产生的哲学背景作了辨析，认为现象学和存在主义哲学思潮在某种程度上对反阐释理论产生了一定的影响；再从60年代之后，后现代主义对现代性的批判与美国的&反文化&潮流两方面追寻反阐释理论产生与发展的内在逻辑；然后又概括介绍了阿兰·罗伯—格里耶、罗兰·巴尔特、苏珊·桑塔格、米歇尔·福科、雅克·德里达、吉尔·德勒兹、让·博德里亚等几位对反阐释理论发生过重要影响的后现代大家，指出&反对阐释&不只是一种文学批评主张，还是一种文化批判理论，它对传统的颠覆与反叛姿态使它不可避免地走向了&解构主义&的逻辑。

A multi-level power laser writing control method based on industry standard architecture bus interface and complex programmable logic device technique for multi-level mastering system is described in this paper.

描述了多阶母盘刻录系统中一种基于工业标准结构总线接口和复杂可编程逻辑器件技术的激光多功率写入控制方法及其控制电路的设计实现。

The low power design example applied in a real design is given out in logic level and the circuit level.

在逻辑级、电路级列举了实际设计中考虑到降低系统功耗以后的例子。

In this paper, data are transformed from data level to logic area level as the interpolation granularity.

为解决上述问题，首次将RFID数据从数据层抽象到逻辑区域层作为处理的粒度，提出3 种基于动态概率路径事件模型的数据填补算法，通过挖掘已知的区域事件的顺序相关性来对后续发生的事件进行判断

On the design of algorithms, a novel exact hierarchical delay analysis method for general circuits is proposed; based on the sensitization theorem for sequential circuits, an exact minimizing clocking method is proposed; based on Boolean process, a waveform simulation method considering interconnecting delay for logic circuit and a parallel waveform simulation method are proposed; a new method that transforms bit-level waveform polynomial to word-level polynomial model is proposed; a multiple valued synthesis algorithm based on multiple valued Boolean process and a wire-centered delay synthesis policy are proposed, in which timing planning, floorplanning, wire planning and optimal clock skew in early design are considered; a two-layers channel routing method for minimizing crosstalk under grid mode is proposed; based on the transition numbers theorems for waveform polynomial, a new method for generation of test with noise effects is proposed.

算法设计方面，提出了一种精确的通用电路层次化延时分析方法；基于时序电路的敏化定理提出时序电路最小时钟周期精确确定方法；提出基于Boolean过程论的考虑互连延迟的逻辑电路波形模拟方法，在分析了波形模拟适合并行化基础上，进一步提出一种并行波形模拟算法；提出一种将位级电路波形多项式描述转化成字级多项式描述的新方法；提出一种基于多值Boolean过程的多值电路综合算法以及一种将前期设计定时规划、前期设计的布局规划和线网结构化方法及低偏移的时钟分配等技术相结合的面向互连延时的综合策略；提出一种串绕最小化的网格模式下的双层通道布线方法；从波形多项式描述跳变数的定理出发提出了一种考虑噪声效应的测试生成新方法。

It has to be computed by the host for the actual clock rate.

主控制器可以用来计算实际的时钟速率。

Let's see what you got.

让我看看你的东西