查询词典 instruction register

And based on traditional graph coloring register allocation,a new algorithm to construct unified and simplified interference graph utilizing complementary predicate is presented,which can reduce spill code.

最后在YHFT-DSP/700芯片的编译器上对所提优化方法的有效性进行了验证。1引言指令级并行(ILP，Instruction Level Parallelism)一直以来都是编译领域的一个研究热点。

Based on a lot of experiment results, a conclusion is drawn: comparing with other factors, the performance of branch handling strategy is the key limits of processor to exploit the instruction level parallelism existed in nonscientific code, cache miss have severe effect on superscalar processor's performance when it runs scientific code. Second, in order to reduce the branch penalty and improve the performance of superscalar processor, a new branch handling strategy—a classification based hierarchical branch handling strategy, CHBHS is proposed. It first expands the traditional processor architecture to support multiple condition code, conditional execution and Mbranch instruction, as a result, compiler can reduce the number of static conditional branch when the code is generated. Then, CHBHS tries to use the best suitable mechanism to deal with different branch base on their different behavior. CHBHS can predict the target address of unconditional branch, subroutine call and conditional branch by buffering their target address in branch target buffer, a newly proposed high efficient return address stack is used to reduce the penalty of subroutine return instruction, a new Counter Register Stack is also proposed to reduce the penalty of loop-closing branch to zero, and dynamic branch predictor is incorporate with branch target buffer to predict the outcome of conditional branch.

基于上述结论，为了尽量消除转移指令对处理器开发指令级并行性能力的影响，进一步提高处理器性能，在详尽分析目前已存在的转移处理策略的特点与局限性的基础上，首次提出了一种新的转移处理策略即基于分类的层次转移处理策略CHBHS(Classification Based Hierarchical Branch Handling Strategy)，它首先通过扩展传统的体系结构，支持多条件码、条件式执行及多分支转移技术，以使编译程序在进行代码生成时可尽量少生成条件转移指令，从而减少静态条件转移指令的数目；其次，基于不同的转移指令的行为不同这一事实，提出了对不同的转移指令采用不同的机制进行处理的思想，即对无条件转移指令和函数调用指令以及条件转移指令的目标地址，采用转移目标缓冲器来预测，对于函数返回指令，采用所提出一种的高效返回地址栈来预测其目标地址，对于大多数循环控制转移指令，采用所提出的Counter Register Stack来将其所可能带来的损失减少为0，对于其他的条件转移指令采用动态预测机制来预测其方向。

To improve data transmission rate of JTAG interface, instruction register and related control logic are redesigned.

为了提高JTAG接口的数据传输效率，指令寄存器和相关控制逻辑被重新设计。

An 8-bit instruction register can only specify 256 different operations and variations on operations.

一个八位的指令寄存器也只能确定256种不同的操作以及对于这些操作的修改。

At this point the instruction register contains the instruction to be executed and the control unit increments the program counter.

此时指导寄存器包含要运行的指导和控制单位增量计画柜台。

Clock line, as well as the bits from the instruction register.

进入到指令解码器的是来自测试寄存器和时钟线的二进制码元。

Decode the instruction stored in the instruction register.

把存贮在指令寄存器内的指令解码。

Commentary: ICWS'86 clearly states the use of an instruction register, but the other operand address and value registers are only implied.

注释： ICWS'86清楚说明指令寄存器的使用，但其他操作数地址和数值寄存器都只是隐含的。

The Instruction Register holds the bit pattern that represents the current instruction; different parts of the bit pattern are used to encode the "operation code" and the address of any data required.

指令寄存器保持着二进制位组合格式表示的当前正在执行的指令。在这个二进制位组合格式中，不同的部分被相应的用来编码"操作代码"以及操作所需数据的地址。

There are several types of registers ,Including an instruction register , which holds the instruction being executed ,an address register, which holds the addresses of data to be processed ;a program register , which holds status information ; and an accumulator , which holds the results of the ALU's

寄存器有几种类型，包括指令寄存器，它含有将要被执行的指示，地址寄存器，它包含被处理的数据地址；程序寄存器，它包含程序的状态信息；还有累加器，它包含算术\逻辑运算单元的操作结果。

Methods: Five patients with parkinsonism or dystonia were assigned to general anesthesia using an modified endotracheal tube.

本实验依照人体实验之相关规定进行，五位患有帕金森氏症或肌张力异常的病人接受神经立体定位手术。

If you can benefit from this book, it is our honour.

如果您能从本书获益，这将是我们的荣幸。