查询词典 hardware interface

C++ also supports several inherently nonportable features including bit-fields and volatile, which make it easier to interface to hardware, and linkage directives, which make it easier to interface to programs written in other langauges.

C++ 还支持几种固有的不可移植的特征，包括位域和 volatile（它们可使与硬件接口更容易）以及链接指示（它使得与用其他语言编写的程序接口更容易）。

All business logic components are based on DCOM. It provides the Business Process Reengineering function, and output/input interfaces based on XML in order to exchange data with different operating system and platform. The system adopts dual encryption with software and hardware: Encapsulating the function of CryptoAPI of Microsoft provides file enciphering interface and file deciphering interface.

本系统采用软加密和硬加密结合的方式来保护软件：封装微软加密库，形成加密、解密组件，提供加密接口和解密接口函数；采用Access库的安全机制，对数据库建立SqServer.mdb三级安全机制；将用户数量写入硬件加密狗中，控制客户端的数量。

The system adopts dual encryption with software and hardware: Encapsulating the function of CryptoAPI of Microsoft provides file enciphering interface and file deciphering interface.

本系统采用软加密和硬加密结合的方式来保护软件：封装微软加密库，形成加密、解密组件，提供加密接口和解密接口函数；采用Access库的安全机制，对数据库建立SqServer.mdb三级安全机制；将用户数量写入硬件加密狗中，控制客户端的数量。

The whole text designs the demand system in two parts of the hardware and software by divided several parts, that include the transplantation of the μ c/ OS-Ⅱembedded operate system transplanting into the ARM microprocessor , the communication of the USB interface in PC, the transplantation of the FAT16 file system transplanting into the μ c/ OS-Ⅱ embedded operate system, and the program design of the man-machine interface and the digital audio-frequency decoding.

全文从硬件和软件两个部分，分多个模块来安排设计我所要求的系统，其中包括μc/OS-Ⅱ嵌入式操作系统在ARM微处理器上的移植，与上位机上USB接口的通讯，FAT16文件系统在μc/OS-Ⅱ嵌入式操作系统上的移植，以及人机界面和数字音频解码的程序设计等。

Moreover, this paper introduces the analysis and design of automation system of the production line at length, including the spot controlling unit, the central controlling unit, hardware and software, communication connecting and electricalcontrol. Also introduces the technique analysis and controlling method design of the raw material preparation, rotating kiln system and coal powder preparation. Describes the system design in detail, such as the main control interface, the system main interface, the system flow diagram, group start and stop, equipments selecting, emergency and fault reset, alarming picture, tendency picture, speed setting, raw material feeding, feeding operation, production reporting table and so on.

接着，论文对该生产线自动控制系统进行了详细地设计分析，包括现场控制部分、中央控制部分、软硬件部分、通讯连接部分和电气控制部分；对生料制备系统、回转窑系统和煤粉制备系统进行了工艺分析和控制方法的设计；并对系统主要控制界面，系统主界面、系统流程图、组起/组停、设备选择、故障复位、故障紧停故障消音、报警画面、阀门操作、趋势画面、转速设定、生料喂料、喂煤操作、原料喂料、生产报表等做了设计介绍。

MAX1999EEI Pinout: 8- to 32-bit and 16- to 32-bit word packing options Programmable wait state options: 2 to 31 CCLK Digital audio interface includes six serial ports, two pre- cision clock generators, an input data port, three programmable timers and a signal routing unit Serial ports provide: Six dual data line serial ports that operate at up to 50 Mbits/s for a 200 MHz core on each data line each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair Left-justified sample pair and I2S support, programmable direction for up to 24 simultaneous receive or transmit channels using two I2S compatible stereo devices per serial port TDM support for telecommunications interfaces including 128 TDM channel support for telephony interfaces such as H.100/H.110 Up to 12 TDM stream support, each with 128 channels per frame Companding selection on a per channel basis in TDM mode Input data port provides an additional input path to the DSP core configurable as either eight channels of I2S or serial data or as seven channels plus a single 20-bit wide syn- chronous parallel data acquisition port Supports receive audio channel data in I2S, left-justified sample pair, or right-justified mode Signal routing unit provides configurable and flexible connections between all DAI components, six serial ports, an input data port, two precision clock generators, three timers, 10 interrupts, six flag inputs, six flag outputs, and 20 SRU I/O pins Serial peripheral interface Master or slave serial boot through SPI Full-duplex operation Master-slave mode multimaster support Open drain outputs Programmable baud rates, clock polarities, and phases 3 Muxed Flag/IRQ lines 1 Muxed Flag/Timer expired line ROM based security features: JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multi- plier/divider ratios JTAG background telemetry for enhanced emulation features IEEE 1149.1 JTAG standard test access port and on-chip emulation Dual voltage: 3.3 V I/O, 1.2 V core Available in 136-ball BGA and 144-lead LQFP packages Lead free packages are also available

MAX1999EEI引脚说明： 8 - 32位和16 - 32位字包装选择可编程等待状态的选择：2至31个CCLK数字音频接口包括6个串行端口，两个前643时钟发生器，输入数据端口， 3可编程定时器和一个信号路由单元串行端口提供：六双串口数据线，在高达50 Mbps的操作/为200兆赫的每个数据行每个人都有一个时钟，帧同步的核心秒，和两个数据可以作为任何一个接收器或发射器对左对齐和I2S配对样本的支持下，最多可同时接收或传送24个频道，每使用两个系列的I2S兼容立体声设备配置可编程方向线；港口的TDM通信接口，包括支持128个电话接口的TDM的渠道，如H.100/H.110支持多达12个的TDM流的支持下，每帧128个频道每个压缩扩展每通道的基础上选择在TDM模式输入数据端口提供了一个额外的输入路径的DSP核心配置为I2S或串行数据或7加一个20位宽的SYN -异步的并行数据采集接口通道或8通道；支持接收通道I2S音频数据，左对齐样本对，或右对齐模式信号路由单元组件之间提供所有戴配置和灵活的连接，6个串行端口，一个输入数据端口，两个精密时钟发生器，3个定时器，10个中断，六旗投入，产出6个旗，20曼谷南南区域股的I / O管脚串行外设接口的硕士或奴隶通过SPI串行启动全双工运作主从模式多主机支持开漏输出可编程波特率，时钟极性和第三期合并调制旗/ IRQ线路1合并调制旗/定时器过期线光盘的防伪特征：JTAG的访问与64位受保护的关键允许内存内存可分配给程序访问控制的限制下对敏感地区有一个代码锁相环/遥测分比率为背景的JTAG仿真功能增强的IEEE 1149.1 JTAG标准测试访问端口的软件和硬件多钳各种各样和片上仿真双电压：3.3六/输出，可在1.2 V核心136球BGA封装和144引脚LQFP封装无铅封装，也可

TDA4864 Pinout: 8- to 32-bit and 16- to 32-bit word packing options Programmable wait state options: 2 to 31 CCLK Digital audio interface includes six serial ports, two pre- cision clock generators, an input data port, three programmable timers and a signal routing unit Serial ports provide: Six dual data line serial ports that operate at up to 50 Mbits/s for a 200 MHz core on each data line each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair Left-justified sample pair and I2S support, programmable direction for up to 24 simultaneous receive or transmit channels using two I2S compatible stereo devices per serial port TDM support for telecommunications interfaces including 128 TDM channel support for telephony interfaces such as H.100/H.110 Up to 12 TDM stream support, each with 128 channels per frame Companding selection on a per channel basis in TDM mode Input data port provides an additional input path to the DSP core configurable as either eight channels of I2S or serial data or as seven channels plus a single 20-bit wide syn- chronous parallel data acquisition port Supports receive audio channel data in I2S, left-justified sample pair, or right-justified mode Signal routing unit provides configurable and flexible connections between all DAI components, six serial ports, an input data port, two precision clock generators, three timers, 10 interrupts, six flag inputs, six flag outputs, and 20 SRU I/O pins Serial peripheral interface Master or slave serial boot through SPI Full-duplex operation Master-slave mode multimaster support Open drain outputs Programmable baud rates, clock polarities, and phases 3 Muxed Flag/IRQ lines 1 Muxed Flag/Timer expired line ROM based security features: JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multi- plier/divider ratios JTAG background telemetry for enhanced emulation features IEEE 1149.1 JTAG standard test access port and on-chip emulation Dual voltage: 3.3 V I/O, 1.2 V core Available in 136-ball BGA and 144-lead LQFP packages Lead free packages are also available

TDA4864引脚说明： 8 - 32位和16 - 32位字包装选择可编程等待状态的选择：2至31个CCLK数字音频接口包括6个串行端口，两个前643时钟发生器，输入数据端口， 3可编程定时器和一个信号路由单元串行端口提供：六双串口数据线，在高达50 Mbps的操作/为200兆赫的每个数据行每个人都有一个时钟，帧同步的核心秒，和两个数据可以作为任何一个接收器或发射器对左对齐和I2S样本对支持，最多可同时接收或传送24个频道，每使用两个系列的I2S兼容立体声设备配置可编程方向线；港口的TDM通信接口，包括支持128个电话接口的TDM的渠道，如H.100/H.110支持多达12个的TDM流的支持下，每帧128个频道每个压缩扩展每通道的基础上选择在TDM模式输入数据端口提供了一个额外的输入路径的DSP核心配置为I2S或串行数据或7加一个20位宽的SYN -异步的并行数据采集接口通道或8通道；支持接收通道I2S音频数据，左对齐样本对，或右对齐模式信号路由单元组件之间提供所有戴配置和灵活的连接，6个串行端口，一个输入数据端口，两个精密时钟发生器，3个定时器，10个中断，六旗投入，产出6个旗，20曼谷南南区域股的I / O管脚串行外设接口的硕士或奴隶通过SPI串行启动全双工运作主从模式多主机支持开漏输出可编程波特率，时钟极性和第三期合并调制旗/ IRQ线路1合并调制旗/定时器过期线光盘的防伪特征：JTAG的访问与64位受保护的关键允许内存内存可分配给程序访问控制的限制下对敏感地区有一个代码锁相环/分比率背景遥测的JTAG仿真功能增强的IEEE 1149.1 JTAG标准测试访问端口软件和硬件多钳各种各样和片上仿真双电压：3.3六/输出，可在1.2 V核心136球BGA封装和144引脚LQFP封装无铅封装，也可

On the other hand,interface reaction is weakened drasticallyon the interface between Co with sulfur-passivated GaAs(100)by CH3CSNH2 treatment,astable interface forms at the coverage of 8〓Ga atoms bonded with S at the surface exchangewith Co atoms and diffuse into Co matrix,which causes the formation of Co-S bonding.

另一方面，对于Co与CH3CSNH2处理的S硫化GaAs(100)表面形成的界面，界面反应大为减弱。当Co覆盖层达到〓时，形成稳定的界面。

Results show that the former two were better than the latter two in quality of the interface water; the cobblestone hank was the highest in population of functional microbes in the interface water and in the mud over the interface, and followed by the clay bank, bondstone bank and concrete posts.

结果表明：4种驳岸的界面上覆水质以鹅卵石驳岸和泥岸较好，而石砌驳岸和砼仿木桩驳岸较差；界面上覆水和界面泥样的功能微生物菌群数量都以鹅卵石驳岸最多，泥岸次之，砼仿木桩驳岸最少。

The AHB bus interface design consists of master module interface design and slave module interface design.

AHB总线接口设计划分为主控模块接口设计及从模块接口设计。

Molecular Distillation is a kind of high vacuum distillation method, which is suitable for the separation of high boiling, heat sensitivity and viscidity products.

分子蒸馏技术是一种在高真空条件下进行的连续蒸馏过程，适合于分离高沸点、热敏性及具有生物活性的混合物。

They are to the Noughties what yuppies were to the Eighties .

那在六十年代是时髦的，但在八十年代肯定是过时了