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与 graph 相关的网络例句 [注:此内容来源于网络,仅供参考]

Experiments on multiplier tree and adder tree expressions exhibit running time reduction of 83% to 99%, and 40% to 80% respectively.4. Arithmetic unit check with half adder graph technique: Binary Moment Diagram technique has been used in multiplier equivalence checking.

比如针对加法和乘法连续运算的表达式,算法从实现电路中提取变量顺序和结合顺序并加以利用,实验表明,在验证乘法连续运算的表达式时减少了83%~99%的时间,加法连续运算表达式的验证时间也可减少40%~89%。4。

Based on ZDFV work, the thesis focuses on the following key problems: how to construct an efficient synthesis engine; how to improve the structural similarity of the two designs; how to verify data path designs efficiently; how to use half adder graph to perform arithmetic unit verification; and how to use the hybrid SAT engine in the existing verification flow.

为了解决这个问题,本文作者结合自主研发等价性验证系统的工作,在高效综合引擎的研究与实现、单个模块的相似性研究、数据通路的验证方法、结合半加图的算术单元验证以及基于混合SAT引擎的RTL验证流程等五个方面开展了研究:1。

The algorithm combines the recognition technique of different coding methods in multiplier, the extraction technique of half adder graph in addition circuit, and the recognition technique of half adder tree structure of partial product addition circuit. With the extracted information, the register transfer level synthesis engine can generate a gate netlist that is logically correct and structurally similar to the implementation.

该算法结合了乘法器的编码方式识别技术、加法电路的半加树提取技术和部分积加法电路的架构识别技术来提取乘法电路的实现结构,以此生成与实现电路结构相似且逻辑正确的网表。

Unlike BDD, BMD adds weight on edges and thus reduces the node quantity of the diagram. A new circuit abstraction method, half adder graph was proposed to represent arithmetic circuits during the synthesis period.

结合半加图的算术单元验证:论文研究了基于BMD验证乘法电路的方法,该方法使用矩分解方式,在BMD的边和节点上赋予权重信息,减少了图的节点数。

Choosing the countdown length of Hamilton for the fitness function, using "evolutionary reversal" technique, we give the best path among 20 cities with MATLAB, and also make graph of the optimal value change with iteration in optimization process.

取哈密尔顿长度的倒数为适应度函数,采用"进化逆转"操作技术,运用MATLAB求解得到20个城市间的最佳路径,并做出了寻优过程中最优值随迭代的变化趋势图。

The paper innovatively presents a surface-based DNA algorithm for solving Hamiltonian circuit problem in a nondirectional graph.

首次提出用DNA表面计算模型来解决无向图哈密尔顿回路问题。

A new mapping scheme is used to map matrix to the general OTIS network, that is the matrix mapping scheme, processors are assigned according to Hamiltonian path in the basic graph of OTIS network.

采用一种新映射策略来处理一般OTIS网络结构上的矩阵映射,即矩阵映射策略是根据基图中的哈密尔顿路径来分配处理器的。

For example,the graph in Fig.3-5 is Hamiltonian(a possible path being P→Q→R→S→T→P)but is not quite Eulerian,since any path which includes every dege exactly once(e. g.P→Q→T→P→S→R→Q→S→T)must end up at a vertex different from the initial vertex.

例如,图3-5所示是一个哈密尔顿图(存在一条路P→Q→R→S→T→P)但不是一个欧拉图,这是因为图中任何包含所有边一次且仅一次的路(如P→Q→T→P→ S→R→Q→S→T)都不能回到原出发顶点。

The question whether a graph is hamiltonian seems to be hard to answer.

一个图是否为Hamilton图的问题很难回答。

Compared with the global harmonic mapping method, this approach has the following advantages.(1) The efficiency of the algorithm is greatly improved. The computational cost involved no longer increases exponentially with the number of vertices of the meshes to be fused.(2) The algorithm is robust as the ambiguity in graph structure combination is alleviated.(3) The detail of the cut mesh is fully kept.(4) The topology restriction of the original algorithm is eliminated.

与原有的基于全局调和映射的融合方法相比,新方法的算法效率大幅度提升,求解时间不再随融合模型顶点数的增加而呈指数增长;减少了二维网格拓扑合并中奇异情况出现的概率,提高了算法的稳定性;被剪切网格的细节得到完整保留;消除了原算法对融合区域拓扑的限制。

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