时钟频率

Of course we will still be releasing versions of the Phenom running at higher clock speeds.

当然我们将继续发布工作在更高时钟频率的翼龙版本。

The prime cost of one gate as a result of applying the 65- nm technical process is reduced by 20% in comparison with 90 nm cyclone II, and clock frequency of memory and coefficients is increased from 216 to 260 MHz.

总理的成本一门作为一个结果，运用65 -纳米技术的过程中减少了2 0％，在比较与9 0奈米的C ycloneI I，和时钟频率的内存和系数增加，从2 16到2 60兆赫。

The power consumption can be reduced by using low power MPU,reasonable power supply,proper clock frequency and low power software.

同时，采用低功耗微电子芯片、合理的供电方式、时钟频率和软件低功耗等措施充分降低总功耗。

This kind of technology inmicroprocessor unusual remarkableness, uses for to help the promotionnowadays the processor clock frequency.

这种技术在微处理器中非常的显著，用来帮助提升现今处理器的时钟频率。

The clock frequency and reset threshold voltage are factory trimmed to spe- cific values.

时钟频率和复位阈值电压是工厂微调，固相萃取- cific值。

12MHZ clock frequency of microcontroller used by a switch input, Trigger Timing counts.

详细说明：采用12MHZ时钟频率的单片机，通过一个开关输入，触发定时计数。

We designed the multi-channel delay and pulse adjustment circuit based on CPLD providing a solution to fast gating timing and delay problems in large nuclear physic experiments. Its main function is accepting a negative NIM trigger input, and outputting a pulse with adjustable delay and width. Minimum step accuracy of the delay and the pulse adjustment is 10ns when the system frequency is 100MHz.

针对大型核物理实验中的符合测量、多路时间测量系统中的门控快定时信号等应用的需要，设计了一种多路延迟／脉宽调节电路，主要功能是对输入的多路快信号进行延迟和脉宽调节，支持NIM负信号输入和输出，在系统主时钟频率为100MHz的时候，延迟和脉宽调节的最小步进精度为10ns。

However, some ripe algorithms are not open for keeping them secret. Some open algorithms exist a lot of questions. Based on the nature of the musical signal, an effective algorithm for pitch shifting is presented while maintaining formant characteristics of the unshifted sound.

本文根据音乐的信号的特征，在保持未变调声音的规格特征上，提出了一种有效的变调算法，在具体实现中，为了保证运算的实时快速，采用了TI公司的TMS320C50DSP芯片作为主处理芯片，它的时钟频率是10MHz。

At system level design, we select the feed-forward form to be benefic for stability and linearity design.

在电路设计方面，大的负载电容、高的时钟频率和高的线性度要求是电路设计的难点。

The first level cache is split caches : instruction cache and data cache, each of which is single-cycle cache with direct-mapped organization. The second level cache is a hybrid and multicycle cache with two-way skewed-associative organization.

NRS4000是一个32位的嵌入式RISC产品，时钟频率为20MHz，采用5级流水技术，实现了面向寄存器的指令集（共128条指令），支持了寄存器窗口切换和基于优先级的中断、故障、跟踪、通信等功能，是一个完整的微处理器系统。

In her eyes, because that is the doorway toher heart * the place where love resides.

女人的漂亮必須從她的眼睛中去看，因為那是她心靈的窗戶和愛居住的地方

I will send some postcards to you.

我会向你发送一些明信片。