时钟频率

At 0.5 ns, memory with actual clock rate of 1000 MHz would churn out 512 GB/s, so a slight inaccuracy there.

在0.5纳秒，内存的实际时钟频率为1000兆赫将流失了512 Gb / s的，所以有轻微错误的。

Asynchronous communication for buses was developed to overcom the worst-case clock rate limitations of synchronous systems.

异步通信。总线的异步通信是为了克服同步系统中极差的时钟频率限制而开发的。

The experimental results show that it achieves peak SNR of 80 dB, peak SNDR of 78 dB and dynamic range of 84 dB over a 1 MHz signal band-width when clocked at 128 MHz. It dissipates 9 mW from a 1.8 V supply.

芯片工作在1.8V电源电压和128MHz时钟频率，在1MHz的信号带宽内，调制器的动态范围为84dB，峰值SNR和SNDR分别为80dB和78dB，功耗为9mW。

The 200kHz free-running clock frequency can be externally adjusted or synchronized with an external signal from 100kHz to above 500kHz.

在200kHz的自由运行时钟频率可与外部调整或从100kHz的外部信号同步至500kHz的上面。

This processor works at the clock frequency 3,0 GHz, and its TDP is 125 W.

这一工程的处理器在时钟频率3，0千兆赫，其加TDP是125瓦特

Officially supported bus are only 1333 MHz , but the BIOS Clock frequency generator can goup to 800 MHz.

官方支持巴则只有第1333兆赫，但BIOS的时钟频率发生器可以高达800兆赫。

This granularity is fine enough for all applications because it is quicker than the hardware clock frequency.

这是精细粒度为所有应用是足够的，因为它比硬件时钟频率更快。

Biggest possible clocks frequencies are the slowest logical waydecided by the electric circuit in, also is the essential way.

最大的可能时钟频率是由电路中最慢的逻辑路径决定，也就是关键路径。

This will allow NVIDIA to raise the maximum clock frequency of memory from present 1800 MHz to 2200 MHz.

这将使NVIDIA的提高，最高的时钟频率的内存，从目前的1800兆赫到2200兆赫。

A topdown design of an 8bit RISC MCU is presented, in order to overcome the limitation of MCS51 microcontroller The core is based on Harvard architecture with 16bit instruction length and 8bit data length The performance of the MCU has been greatly improved by introducing singleclockcycle instructions, setting multiple highspeed working registers, replacing microprogram with direct logic block, etc FPGA verification and computer simulation show that its maximum clock frequency and instruction e...

在对传统的MCS51系列单片微控制器的局限性进行分析的基础上，设计了一种基于增强8位RISC构架的微控制器内核。该MCU核采用哈佛结构、16位指令字长和8位数据字长，通过设计单周期指令、在内部设置多个快速寄存器及采用硬布线逻辑代替微程序控制的方法，加快了微处理器的速度，提高了指令的执行效率。计算机仿真验证和FPGA仿真验证的结果表明，该MCU的最高时钟频率和指令执行效率等指标均优于MCS51的5倍以上。

Do not gum up the work by telling mother what we are going to do .

别告诉母亲我们要干的事，那会把事情搞糟的。

In recent years, application of the partial prestressed concrete beam s is developed.

近年来，随着部分预应力砼梁应用的推广，发现我国规范所采用的名义拉应力法的计算结果不稳定。