加法器

This procedure is to use two four parallel binary adder cascade manner through an 8-bit adder.

详细说明：本程序是利用两个4位二进制并行加法器通过级联方式构成一个8位加法器。

We can use software to do most calculation but not use hardware. The most basic circuit doing calculation in the computer is binary adder. For example, we can use of addition to do subtracting, continuous adding to do multiplication, and continuous subtracting to do division.

在电脑的世界里，可以做任何数字系统且复杂的演算，但是大多数的演算都藉由软体来解决，而非用硬体直接进行各种演算，电脑的硬体或其他数位电路在做算术运算时，最基本的电路往往只有二进位加法器而已，至於减法可藉由补数的加法解决，乘法等於连续的加法，除法则是连续的减法，可见加法器在运算数位系统中的重要性。

It analysed the principle of Reed-Solomon encode, the design of basic unit circuit, including Galois field adder and multiplier, and addressed the application method of parallel multiplier with constant coefficients under the natural base.

分析了RS码的编码原理，基本单元电路设计，包括有限域加法器和乘法器，并着重阐述了自然基下常系数并行来法器的实现方法。

In chapter 4, test for M×N-bits CSA array multiplier with a 4-bits CLA adder chain as its last stage and CC multiplier with 4:2 compressor as its basic cell in the compressor part are studied.

基于以上原因，本论文第4章研究了最后一级为4位CLA加法器链的M×N位CSA阵列乘法器和以4∶2压缩器为基本单元的列压缩乘法器的测试问题。

A logic element designed to act as either an adder or a subtracter in accordance with the control signal applied to it.

根据供给它的控制信号，或起加法器作用或起减法器作用的一种逻辑元件。

Modulo adder plays an important role in RNS and it is one of the basic factors for improving the performance of RNS.

本文基于传统二进制中的前缀算法，结合模加法器的基本原理，设计并实现了一种新的模加法器。

This dissertation is based on the prefix algorithm of traditional binary system, combines the basic principle of modulo adder, design and realized one kind of new modulo adder.

本文基于传统二进制中的前缀算法，结合模加法器的基本原理，设计并实现了一种新的模加法器。

A signal processing circuit for improved 2D-PSD including high-precision, low temperature excursion and high input impedance preamplifier, summator, subtracter and divider is used in high-precision laser collimation system.

采用高精度低温漂高输入阻抗的前置放大器、加法器、减法器、除法器等元器件设计了一种改进型2D-PSD的信号调理电路，用于高精度的激光准直系统中。

Because of the requirements for high speed and high precision in adders,redundant signed digit number adders are proposed.

冗余符号数加法器满足了对加法器高速度和高精度的要求。

The result of analysis and comparison with other kind of modulo adders shows that the proposed modulo adder has higher efficient in speed and power consumption than others.

最后，通过与其它模加法器在结构以及算法等方面进行分析比较，表明本文所设计的模加法器性能优异。

Methods: Five patients with parkinsonism or dystonia were assigned to general anesthesia using an modified endotracheal tube.

本实验依照人体实验之相关规定进行，五位患有帕金森氏症或肌张力异常的病人接受神经立体定位手术。

If you can benefit from this book, it is our honour.

如果您能从本书获益，这将是我们的荣幸。