分支指令

Basic block: A sequence of one or more consecutive, executable statements containing no branches.

基本块：一个由不包含任何分支的一个或多个连续的、可执行的指令组成的序列。

This is a good indicator to show that the core is not doing lots of "useful" work since it is working on the wrong branch of instruction stream.

这是一种用于示出核因其正在指令流错的误分支上工作而没有做出许多"有用"工作的良好指示器。

But the uncertainty of instruction flow branch behavior affects the fully development of the pipelines performance, which is solved with the appearance of branch prediction to great extent. Excellent branch prediction technology, which can effectively improve the efficiency of fetching instruction of micro-processor, is the basic guarantee of the improvement of micro-processor.

但指令流分支行为的不确定性影响了流水线性能的充分发挥，分支预测技术的出现在很大程度上解决了这一问题，良好的分支预测技术能有效地提高微处理器的取指效率，是微处理器性能提升的基本保证。

The idea of Autonomous Instruction Memory is to combine Top-Level Instruction Memory and Branch Target Buffer. This kind of architecture has an character of self-generating instruction address.

自主指令记忆体的设计的想法在於结合动态分支预测器和最上层的指令记忆体而拥有自行产生指令位址的特性，因而使得CPU可以不用传送指令位址给自主指令记忆体，而达到降低CPU和自主指令记忆体之间指令位址汇流排上传递资料量的目的。

Based on a lot of experiment results, a conclusion is drawn: comparing with other factors, the performance of branch handling strategy is the key limits of processor to exploit the instruction level parallelism existed in nonscientific code, cache miss have severe effect on superscalar processor's performance when it runs scientific code. Second, in order to reduce the branch penalty and improve the performance of superscalar processor, a new branch handling strategy—a classification based hierarchical branch handling strategy, CHBHS is proposed. It first expands the traditional processor architecture to support multiple condition code, conditional execution and Mbranch instruction, as a result, compiler can reduce the number of static conditional branch when the code is generated. Then, CHBHS tries to use the best suitable mechanism to deal with different branch base on their different behavior. CHBHS can predict the target address of unconditional branch, subroutine call and conditional branch by buffering their target address in branch target buffer, a newly proposed high efficient return address stack is used to reduce the penalty of subroutine return instruction, a new Counter Register Stack is also proposed to reduce the penalty of loop-closing branch to zero, and dynamic branch predictor is incorporate with branch target buffer to predict the outcome of conditional branch.

基于上述结论，为了尽量消除转移指令对处理器开发指令级并行性能力的影响，进一步提高处理器性能，在详尽分析目前已存在的转移处理策略的特点与局限性的基础上，首次提出了一种新的转移处理策略即基于分类的层次转移处理策略CHBHS(Classification Based Hierarchical Branch Handling Strategy)，它首先通过扩展传统的体系结构，支持多条件码、条件式执行及多分支转移技术，以使编译程序在进行代码生成时可尽量少生成条件转移指令，从而减少静态条件转移指令的数目；其次，基于不同的转移指令的行为不同这一事实，提出了对不同的转移指令采用不同的机制进行处理的思想，即对无条件转移指令和函数调用指令以及条件转移指令的目标地址，采用转移目标缓冲器来预测，对于函数返回指令，采用所提出一种的高效返回地址栈来预测其目标地址，对于大多数循环控制转移指令，采用所提出的Counter Register Stack来将其所可能带来的损失减少为0，对于其他的条件转移指令采用动态预测机制来预测其方向。

Conventional BTB is looked up while instruction fetcher is fetching an instruction. The result returned from BTB tells instruction fetcher the address of the next instruction.

一般的分支目标缓冲器是在每次抓取指令时进行存取，并由其结果决定下次从那个位址抓取指令。

For design strategy, speed 200MHz is the goal, and performance-optimized is the main point. Then, improve the mechanisms of adopting instruction pre-fetch, branch prediction, parallel execution, executive path of instruction and operation unit, and compare its results, probe into what's learning from the design.

以时脉速度200MHz为目标来作为设计策略，并将重点放在效能的最佳化部份，使用预先指令提取、分支预测、平行处理、指令执行路径以及计算单元执行路径最佳化等机制中加以改良，比较其结果并且探讨其设计心得。

High-performance RISC CPU · Only 35 single-word instructions to learn - All single-cycle instructions except for program branches which are two-cycle · Operating speed: DC - 20 MHz clock input DC - 200 ns instruction cycle · Interrupt capability (up to 7 internal/external interrupt sources)· 8-level deep hardware stack · Direct, Indirect and Relative Addressing modes

高性能的RISC CPU·只有35单条指令学习-除了程序分支是两个周期·工作速度：直流- 20 MHz的时钟输入DC - 200 ns的所有单周期指令指令周期·中断能力（/外部中断源，高达7内部）·8级深硬件堆栈·直接，间接和相对寻址方式

For more elaborate branchless logic, compilers employ conditional instructions (provided that such instructions are available on the target CPU architecture).

为了更好的实现不包含条件分支的逻辑判断代码，编译器会使用条件指令(这是一种由目标CPU提供的指令)。

MAMO can be used to compute the real performance of microprocessor based on the contribution to CPI of each microprocessor part computed by the above models.

这一模型主要包括指令窗口模型，功能部件受限模型，分支误预测事件模型，指令和数据Cache失效模型。

What are your goals and strategies for growth?

你的成长目标和策略是什么？

And unto the angel of the church in Sardis write; These things saith he that hath the seven irits of God, and the seven star I know thy works, that thou hast a name that thou livest, and art dead.

3：1 你要写信给撒狄教会的使者，说，那有神的七灵和七星的，说，我知道你的行为，按名你是活的，其实是死的。