查询词典 versatile automatic data exchange

The method includes establishing one reverse mapping list comprising list items; reading the mapping data recorded in the data block state list item area to the list items during system initialization; checking reverse mapping list and finding the data block in Flash memory during reading some logic block; and writing the updated data into the empty data area of one new data block, writing the mapping data between the new logic block and the new data block into the state list item area and updating the mapping data of the corresponding list item in the reverse mapping list during writing some logic blcok.

包括：建立一个由表项组成的反向映射表，一个表项对应一个逻辑块；在系统初始化过程中，将数据块状态表项区中记录的映射信息，按逻辑块号与表项间的对应关系读取到各表项中；读取某逻辑块时，以其逻辑块号作为表项索引查找反向映射表，定位到表项，根据表项中记录的映射信息，在Flash存储器件中查找到数据块；写入某逻辑块时，将更新数据写入一新数据块的空白数据区中和将该逻辑块与新数据块间的映射信息写入状态表项区中，同时更新反向映射表相应表项的映射信息。

This invention discloses one data regroup method, which is based on the original independent and redundant RAID system high address to preserve one block disk space as regroup area and to repeat the following steps: a, determining the current regroup data low address and to regroup the data from high address to low address into new RAIN type of data; writing the regroup data from initial address into the new RAID type data; using the current regroup data of low address as the next regroup data high address as the next second initial address of the data.

本发明公开了一种数据重组方法，在原独立冗余磁盘阵列系统高地址侧尾部预留一块磁盘空间作为重组区域，将该预留重组区域的高地址作为写入数据的起始地址，并将原RAID系统中存有数据的高地址作为重组数据的起始高地址；数据重组完之前重复执行以下步骤：确定当前要重组数据的低地址，并将当前要重组数据高地址到低地址之间的数据重组为新RAID类型数据；将重组后的数据从写入数据的起始地址向低地址方向，顺序写入新RAID系统中；当前要重组数据低地址的邻接低地址作为下次要重组数据的高地址，当前写入数据低地址的邻接低地址作为下次写入数据的起始地址。

MAX1999EEI Pinout: 8- to 32-bit and 16- to 32-bit word packing options Programmable wait state options: 2 to 31 CCLK Digital audio interface includes six serial ports, two pre- cision clock generators, an input data port, three programmable timers and a signal routing unit Serial ports provide: Six dual data line serial ports that operate at up to 50 Mbits/s for a 200 MHz core on each data line each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair Left-justified sample pair and I2S support, programmable direction for up to 24 simultaneous receive or transmit channels using two I2S compatible stereo devices per serial port TDM support for telecommunications interfaces including 128 TDM channel support for telephony interfaces such as H.100/H.110 Up to 12 TDM stream support, each with 128 channels per frame Companding selection on a per channel basis in TDM mode Input data port provides an additional input path to the DSP core configurable as either eight channels of I2S or serial data or as seven channels plus a single 20-bit wide syn- chronous parallel data acquisition port Supports receive audio channel data in I2S, left-justified sample pair, or right-justified mode Signal routing unit provides configurable and flexible connections between all DAI components, six serial ports, an input data port, two precision clock generators, three timers, 10 interrupts, six flag inputs, six flag outputs, and 20 SRU I/O pins Serial peripheral interface Master or slave serial boot through SPI Full-duplex operation Master-slave mode multimaster support Open drain outputs Programmable baud rates, clock polarities, and phases 3 Muxed Flag/IRQ lines 1 Muxed Flag/Timer expired line ROM based security features: JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multi- plier/divider ratios JTAG background telemetry for enhanced emulation features IEEE 1149.1 JTAG standard test access port and on-chip emulation Dual voltage: 3.3 V I/O, 1.2 V core Available in 136-ball BGA and 144-lead LQFP packages Lead free packages are also available

MAX1999EEI引脚说明： 8 - 32位和16 - 32位字包装选择可编程等待状态的选择：2至31个CCLK数字音频接口包括6个串行端口，两个前643时钟发生器，输入数据端口， 3可编程定时器和一个信号路由单元串行端口提供：六双串口数据线，在高达50 Mbps的操作/为200兆赫的每个数据行每个人都有一个时钟，帧同步的核心秒，和两个数据可以作为任何一个接收器或发射器对左对齐和I2S配对样本的支持下，最多可同时接收或传送24个频道，每使用两个系列的I2S兼容立体声设备配置可编程方向线；港口的TDM通信接口，包括支持128个电话接口的TDM的渠道，如H.100/H.110支持多达12个的TDM流的支持下，每帧128个频道每个压缩扩展每通道的基础上选择在TDM模式输入数据端口提供了一个额外的输入路径的DSP核心配置为I2S或串行数据或7加一个20位宽的SYN -异步的并行数据采集接口通道或8通道；支持接收通道I2S音频数据，左对齐样本对，或右对齐模式信号路由单元组件之间提供所有戴配置和灵活的连接，6个串行端口，一个输入数据端口，两个精密时钟发生器，3个定时器，10个中断，六旗投入，产出6个旗，20曼谷南南区域股的I / O管脚串行外设接口的硕士或奴隶通过SPI串行启动全双工运作主从模式多主机支持开漏输出可编程波特率，时钟极性和第三期合并调制旗/ IRQ线路1合并调制旗/定时器过期线光盘的防伪特征：JTAG的访问与64位受保护的关键允许内存内存可分配给程序访问控制的限制下对敏感地区有一个代码锁相环/遥测分比率为背景的JTAG仿真功能增强的IEEE 1149.1 JTAG标准测试访问端口的软件和硬件多钳各种各样和片上仿真双电压：3.3六/输出，可在1.2 V核心136球BGA封装和144引脚LQFP封装无铅封装，也可

TDA4864 Pinout: 8- to 32-bit and 16- to 32-bit word packing options Programmable wait state options: 2 to 31 CCLK Digital audio interface includes six serial ports, two pre- cision clock generators, an input data port, three programmable timers and a signal routing unit Serial ports provide: Six dual data line serial ports that operate at up to 50 Mbits/s for a 200 MHz core on each data line each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair Left-justified sample pair and I2S support, programmable direction for up to 24 simultaneous receive or transmit channels using two I2S compatible stereo devices per serial port TDM support for telecommunications interfaces including 128 TDM channel support for telephony interfaces such as H.100/H.110 Up to 12 TDM stream support, each with 128 channels per frame Companding selection on a per channel basis in TDM mode Input data port provides an additional input path to the DSP core configurable as either eight channels of I2S or serial data or as seven channels plus a single 20-bit wide syn- chronous parallel data acquisition port Supports receive audio channel data in I2S, left-justified sample pair, or right-justified mode Signal routing unit provides configurable and flexible connections between all DAI components, six serial ports, an input data port, two precision clock generators, three timers, 10 interrupts, six flag inputs, six flag outputs, and 20 SRU I/O pins Serial peripheral interface Master or slave serial boot through SPI Full-duplex operation Master-slave mode multimaster support Open drain outputs Programmable baud rates, clock polarities, and phases 3 Muxed Flag/IRQ lines 1 Muxed Flag/Timer expired line ROM based security features: JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multi- plier/divider ratios JTAG background telemetry for enhanced emulation features IEEE 1149.1 JTAG standard test access port and on-chip emulation Dual voltage: 3.3 V I/O, 1.2 V core Available in 136-ball BGA and 144-lead LQFP packages Lead free packages are also available

TDA4864引脚说明： 8 - 32位和16 - 32位字包装选择可编程等待状态的选择：2至31个CCLK数字音频接口包括6个串行端口，两个前643时钟发生器，输入数据端口， 3可编程定时器和一个信号路由单元串行端口提供：六双串口数据线，在高达50 Mbps的操作/为200兆赫的每个数据行每个人都有一个时钟，帧同步的核心秒，和两个数据可以作为任何一个接收器或发射器对左对齐和I2S样本对支持，最多可同时接收或传送24个频道，每使用两个系列的I2S兼容立体声设备配置可编程方向线；港口的TDM通信接口，包括支持128个电话接口的TDM的渠道，如H.100/H.110支持多达12个的TDM流的支持下，每帧128个频道每个压缩扩展每通道的基础上选择在TDM模式输入数据端口提供了一个额外的输入路径的DSP核心配置为I2S或串行数据或7加一个20位宽的SYN -异步的并行数据采集接口通道或8通道；支持接收通道I2S音频数据，左对齐样本对，或右对齐模式信号路由单元组件之间提供所有戴配置和灵活的连接，6个串行端口，一个输入数据端口，两个精密时钟发生器，3个定时器，10个中断，六旗投入，产出6个旗，20曼谷南南区域股的I / O管脚串行外设接口的硕士或奴隶通过SPI串行启动全双工运作主从模式多主机支持开漏输出可编程波特率，时钟极性和第三期合并调制旗/ IRQ线路1合并调制旗/定时器过期线光盘的防伪特征：JTAG的访问与64位受保护的关键允许内存内存可分配给程序访问控制的限制下对敏感地区有一个代码锁相环/分比率背景遥测的JTAG仿真功能增强的IEEE 1149.1 JTAG标准测试访问端口软件和硬件多钳各种各样和片上仿真双电压：3.3六/输出，可在1.2 V核心136球BGA封装和144引脚LQFP封装无铅封装，也可

This invention discloses a power control method based on mixed automatic retransmitting mechanism in which the user end checks received data packet and to feed back to the base station ACK message if the result is correct, and the base station sends the next data packet according to the emitting power of last data packet, if not, sends back NA CK message and quality information of received data packet, the base station will adjust the transmitting power of retransmitting data packet and retransmits the said data packet to guarantee the retransmitting efficiency of the data packet, reduce resource lost of the system to the ulmost and reduce signal interference among different users.

本发明公开了一种基于混合自动重传机制的功率控制方法，该方法通过用户端对接收到的数据包进行校验，当结果正确时，向基站反馈ACK消息，由基站按照上一个数据包的发射功率发送下一个数据包，否则，向基站反馈NACK消息，以及接收到的数据包的质量信息，基站根据所述数据包的质量信息，调整重传数据包的发射功率，并重新发送所述数据包，采用上述方案对发送失败的数据包重传时根据数据包的总质量信息配以不同的发射功率，从而可以在保证数据包重传效率的基础上，最大限度地减少系统的资源消耗，减少不同用户之间的信号干扰。

This invention discloses a power control method based on mixed automatic retransmitting mechanism in which the user end checks received data packet and to feed back to the base station ACK message if the result is correct, and the base station sends the next data packet according to the emitting power of last data packet, if not, sends back NA CK message and quality information of received data packet, the base station will adjust the transmitting power of retransmitting data packet and retransmits the said data packet to guarantee the retransmitting efficiency of the data packet, reduce resource lost of the system to the ulmost and reduce signal interference among different users.

抜粋 本发明公开了一种基于混合自动重传机制的功率控制方法，该方法通过用户端对接收到的数据包进行校验，当结果正确时，向基站反馈ACK消息，由基站按照上一个数据包的发射功率发送下一个数据包，否则，向基站反馈NACK消息，以及接收到的数据包的质量信息，基站根据所述数据包的质量信息，调整重传数据包的发射功率，并重新发送所述数据包，采用上述方案对发送失败的数据包重传时根据数据包的总质量信息配以不同的发射功率，从而可以在保证数据包重传效率的基础上，最大限度地减少系统的资源消耗，减少不同用户之间的信号干扰。

This invention discloses a power control method based on mixed automatic retransmitting mechanism in which the user end checks received data packet and to feed back to the base station ACK message if the result is correct, and the base station sends the next data packet according to the emitting power of last data packet, if not, sends back NA CK message and quality information of received data packet, the base station will adjust the transmitting power of retransmitting data packet and retransmits the said data packet to guarantee the retransmitting efficiency of the data packet, reduce resource lost of the system to the ulmost and reduce signal interference among different users.

要约 本发明公开了一种基于混合自动重传机制的功率控制方法，该方法通过用户端对接收到的数据包进行校验，当结果正确时，向基站反馈ACK消息，由基站按照上一个数据包的发射功率发送下一个数据包，否则，向基站反馈NACK消息，以及接收到的数据包的质量信息，基站根据所述数据包的质量信息，调整重传数据包的发射功率，并重新发送所述数据包，采用上述方案对发送失败的数据包重传时根据数据包的总质量信息配以不同的发射功率，从而可以在保证数据包重传效率的基础上，最大限度地减少系统的资源消耗，减少不同用户之间的信号干扰。

An embodiment of the invention discloses an automatic retransmission requesting method in a relay network. The method comprises the following procedures: storing the data and transmitting the data to the receiving end when a relay station RS confirms that the data from the transmitting side is correctly received; returning an affirmative response of the corresponding data to the transmitting side by the RS when the RS confirms that the data corresponding to the response information is correctly received by the receiving end according to the response information from the receiving end; and retransmitting the corresponding data when the RS confirms that the data stored by itself is not correctly received by the receiving end according to the response information.

本发明实施例公开了一种中继网络中的自动重传请求方法，该方法包括：中继站RS确定正确接收到来自发端的数据时，保存所述数据，将所述数据转发给收端；所述RS根据来自所述收端的应答信息，确认所述应答信息对应的数据已被所述收端正确接收，则向所述发端返回对应数据的肯定应答；所述RS根据所述应答信息确定自身已保存的数据未被所述收端正确接收，则向所述收端重传对应数据。

So called "likely is" is for under the seriously restricted condition of simple labor and commodity exchange in the early days, both sides know about the approximate labor amount needed for producing the article for exchanging, so it is relatively easy to realize the equate labor exchange; So called "likely not" is for in the process of developed and complicated commodity exchange, it is very difficult for the dealers to compute the labor amount that includes in the article of other side, so the principle of equate labor exchange actually does not inheres the meaning that prevalently use, the comparing interests principle can be the principle that prevalently use, but the equate labor exchange principle just is a kind of special example of comparing interests principle.

所谓&似是&是因为在初期简单劳动及其商品交换的严格限制条件下，双方都知道要生产所交换的商品需要的大致劳动量，等量劳动交换的实现比较容易；所谓&而非&，则是因为在发达复杂的商品交换中，交换者很难统一计量出对方商品所包含的劳动量，等量劳动交换原则事实上就不具有普遍适用的意义。商品交换的比较利益原则才是普遍适用的原则，等量劳动交换原则只是比较利益原则的一种特例。

As to domestic sector, the author discuss the influences of different exchange rate regime on growth, inflation, economic stability and financial deepening, and agues that:(1) the relatively fixed exhange rate regimes are more pro-growth for emerging economies;(2) the relatively fixed exchange rate regimes can be useful for control of inflation in developing countries, but it can also be replaced by other monetary rules like inflaiton-targeting;(3) fixed exchange rate regime woulde better to deal with nominal shocks when floating exchange rate regime better to deal with real shocks, but both of them can not entirely insulate the external shocks;(4) the improvement of financial deepening is faster under relative fixed exchange rate regimes.

从国内经济部门看，不同汇率制度对经济增长、通货膨胀、经济稳定、金融深化等关键变量具有不同影响：（1）对于新兴市场国家来说，相对固定的汇率制度更有利于促进经济增长；（2）相对固定的汇率制度有利于抑制通货膨胀，但也可以由其他货币规则替代；（3）固定汇率更适合应对名义经济冲击，浮动汇率更适合应对实际经济冲击，二者都不能隔离外部冲击；（4）在相对固定的汇率制度下，金融深化发展更快。

"The operators will suffer a temporary decrease in the number of consumers and short message services as people may not like having to provide their ID cards for a phone number," Xu Junqi, vice-dean with the Policy-Making Institute of the Telecommunications Research Centre under MII, said yesterday.

信息产业部下属的通信决策研究院副主任徐俊其昨天说：&实行手机实名制后，人们可能不太情愿用身份证注册手机号，所以通信运营商会暂时面临用户减少和短信用户减少的问题。&

I don't believe in make-believe!

我不相信这些虚构的故事。