查询词典 interrupt level

The set of programs stored in ROM is traditionally called the Basic Input/Output System in the 80 x 86 architecture, because it includes several interrupt-driven low-level procedures used by all operating systems in the booting phase to handle the hardware devices that make up the computer.

而这些ROM中的程序就是通常80x86体系结构中所说的BIOS，它包含了一些以中断驱动的底层过程，在引导阶段操作系统利用这些过程控制那些启动计算机的硬件设备。

Aiming at this target, this paper presents a new approach, which adopts special keyboard and nixie tube driven chip and I2C bussing technique in hardware design, and three level interrupt priority software structure in software design.

针对以上目标，该研究在硬件设计上采用专用键盘扫描与数码管驱动芯片ZLG7290和I2C总线技术，软件设计上采用三级中断优先级软件结构，使得控制系统很好地达到了设计目标。

The system can schedule at interrupt service level and thus responsive property of system is improved accordingly.

时钟作为操作系统的脉搏，是协调系统运作的一个重要依据，一般系统的时钟频率是固定的。

It is a global masking process for any interrupt of level higher than n.

对于比n更高的任何中断级来说，这是一个总的屏蔽处理。

Wire the lines to any other port, as long as D+ is also wired to INT0 or anyother hardware interrupt, as long as it is the highest level interrupt, see

你也可以连接到其他的极口，只要是D+也是连接到INT0（或其他硬件中断，只要是最高级别的中断

54LS75 Pinout: Note that the level 7 interrupt is also level sensitive, and must be held until a level 7 IACK begins.

54LS75引脚说明：请注意，7级中断也是敏感程度，必须要等到一个7级亚克开始举行。

In ChibiOS/RT the counting semaphores are mainly meant as a synchronization mechanism between interrupt handlers and high level code running at thread level.

在ChibiOS/RT中计数信号量多数情况下表示的是在中断服务与线程层面上的高级代码之间的同步机制。

In the development of the home's inside receive/send controller , the two level interrupt receive device , which was compose of interrupt controller , was adopted to realize the home's digital signals' collection , the A/D converter was adopted to realize the home's digital signals' collection . The A/D converter was adopted to realize the home's analog signals' collection .

在家庭智能化内部收发控制器的设计中，采用中断控制器组成二级中断接收装置实现对家庭数字信号的采集，采用A/D转换器实现对家庭模拟信号的采集，采用译码器实现对数字信号的传出。

High-performance RISC CPU · Only 35 single-word instructions to learn - All single-cycle instructions except for program branches which are two-cycle · Operating speed: DC - 20 MHz clock input DC - 200 ns instruction cycle · Interrupt capability (up to 7 internal/external interrupt sources)· 8-level deep hardware stack · Direct, Indirect and Relative Addressing modes

高性能的RISC CPU·只有35单条指令学习-除了程序分支是两个周期·工作速度：直流- 20 MHz的时钟输入DC - 200 ns的所有单周期指令指令周期·中断能力（/外部中断源，高达7内部）·8级深硬件堆栈·直接，间接和相对寻址方式

Pinout: C High-performance 32-bit RISC Architecture C High-density 16-bit Instruction Set C Leader in MIPS/Watt C Little-endian C Embedded ICE (In-circuit Emulation) 8-, 16- and 32-bit Read and Write Support 256K Bytes of On-chip SRAM C 32-bit Data Bus C Single-clock Cycle Access Fully Programmable External Bus Interface C Maximum External Address Space of 64M Bytes C Up to Eight Chip Selects C Software Programmable 8/16-bit External Data Bus Eight-level Priority, Individually Maskable, Vectored Interrupt Controller C Four External Interrupts, including a High-priority, Low-latency Interrupt Request 32 Programmable I/O Lines Three-channel 16-bit Timer/Counter C Three External Clock Inputs C Two Multi-purpose I/O Pins per Channel Two USARTs C Two Dedicated Peripheral Data Controller Channels per USART Programmable Watchdog Timer Advanced Power-saving Features C CPU and Peripheral Can be Deactivated Individually Fully Static Operation: C 0 Hz to 75 MHz Internal Frequency Range at VDDCORE = 1.8V, 85C 2.7V to 3.6V I/O Operating Range 1.65V to 1.95V Core Operating Range -40C to +85C Temperature Range Available in 100-lead TQFP Package

M5L8253P-5引脚说明： C型高性能32位RISC架构C高密度以MIPS /瓦C小端C十六位指令集C领袖嵌入式冰8 - 16 -位和32位的读写支持256K的片上SRAM的 32位数据总线C单时钟周期存取字节完全可编程的外部总线接口C最大的外部地址空间的64M字节多达8个C芯片选择C软件可编程8位外部数据总线8级优先级，独立可屏蔽，向量中断控制器C四外部中断，其中包括一个高优先级，低延迟中断要求32个可编程I / O口线三通道16位定时器/计数器C三个外部时钟输入C两多用途I / O引脚每通道2个通用同步C两专用外设数据控制器通道每个USART可编程看门狗定时器先进的节能特性 CPU和外设可停用独立全静态工作中：C 0 Hz至75 MHz的频率范围内的VDDCORE = 1.8，85℃2.7V到3.6VI / O的操作1.65V到1.95V范围核心工作电压范围在- 40C至+85 C温度范围内使用的100引脚TQFP封装

Methods: Five patients with parkinsonism or dystonia were assigned to general anesthesia using an modified endotracheal tube.

本实验依照人体实验之相关规定进行，五位患有帕金森氏症或肌张力异常的病人接受神经立体定位手术。

If you can benefit from this book, it is our honour.

如果您能从本书获益，这将是我们的荣幸。