查询词典 input current

MAX1999EEI Pinout: 8- to 32-bit and 16- to 32-bit word packing options Programmable wait state options: 2 to 31 CCLK Digital audio interface includes six serial ports, two pre- cision clock generators, an input data port, three programmable timers and a signal routing unit Serial ports provide: Six dual data line serial ports that operate at up to 50 Mbits/s for a 200 MHz core on each data line each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair Left-justified sample pair and I2S support, programmable direction for up to 24 simultaneous receive or transmit channels using two I2S compatible stereo devices per serial port TDM support for telecommunications interfaces including 128 TDM channel support for telephony interfaces such as H.100/H.110 Up to 12 TDM stream support, each with 128 channels per frame Companding selection on a per channel basis in TDM mode Input data port provides an additional input path to the DSP core configurable as either eight channels of I2S or serial data or as seven channels plus a single 20-bit wide syn- chronous parallel data acquisition port Supports receive audio channel data in I2S, left-justified sample pair, or right-justified mode Signal routing unit provides configurable and flexible connections between all DAI components, six serial ports, an input data port, two precision clock generators, three timers, 10 interrupts, six flag inputs, six flag outputs, and 20 SRU I/O pins Serial peripheral interface Master or slave serial boot through SPI Full-duplex operation Master-slave mode multimaster support Open drain outputs Programmable baud rates, clock polarities, and phases 3 Muxed Flag/IRQ lines 1 Muxed Flag/Timer expired line ROM based security features: JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multi- plier/divider ratios JTAG background telemetry for enhanced emulation features IEEE 1149.1 JTAG standard test access port and on-chip emulation Dual voltage: 3.3 V I/O, 1.2 V core Available in 136-ball BGA and 144-lead LQFP packages Lead free packages are also available

MAX1999EEI引脚说明： 8 - 32位和16 - 32位字包装选择可编程等待状态的选择：2至31个CCLK数字音频接口包括6个串行端口，两个前643时钟发生器，输入数据端口， 3可编程定时器和一个信号路由单元串行端口提供：六双串口数据线，在高达50 Mbps的操作/为200兆赫的每个数据行每个人都有一个时钟，帧同步的核心秒，和两个数据可以作为任何一个接收器或发射器对左对齐和I2S配对样本的支持下，最多可同时接收或传送24个频道，每使用两个系列的I2S兼容立体声设备配置可编程方向线；港口的TDM通信接口，包括支持128个电话接口的TDM的渠道，如H.100/H.110支持多达12个的TDM流的支持下，每帧128个频道每个压缩扩展每通道的基础上选择在TDM模式输入数据端口提供了一个额外的输入路径的DSP核心配置为I2S或串行数据或7加一个20位宽的SYN -异步的并行数据采集接口通道或8通道；支持接收通道I2S音频数据，左对齐样本对，或右对齐模式信号路由单元组件之间提供所有戴配置和灵活的连接，6个串行端口，一个输入数据端口，两个精密时钟发生器，3个定时器，10个中断，六旗投入，产出6个旗，20曼谷南南区域股的I / O管脚串行外设接口的硕士或奴隶通过SPI串行启动全双工运作主从模式多主机支持开漏输出可编程波特率，时钟极性和第三期合并调制旗/ IRQ线路1合并调制旗/定时器过期线光盘的防伪特征：JTAG的访问与64位受保护的关键允许内存内存可分配给程序访问控制的限制下对敏感地区有一个代码锁相环/遥测分比率为背景的JTAG仿真功能增强的IEEE 1149.1 JTAG标准测试访问端口的软件和硬件多钳各种各样和片上仿真双电压：3.3六/输出，可在1.2 V核心136球BGA封装和144引脚LQFP封装无铅封装，也可

TDA4864 Pinout: 8- to 32-bit and 16- to 32-bit word packing options Programmable wait state options: 2 to 31 CCLK Digital audio interface includes six serial ports, two pre- cision clock generators, an input data port, three programmable timers and a signal routing unit Serial ports provide: Six dual data line serial ports that operate at up to 50 Mbits/s for a 200 MHz core on each data line each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair Left-justified sample pair and I2S support, programmable direction for up to 24 simultaneous receive or transmit channels using two I2S compatible stereo devices per serial port TDM support for telecommunications interfaces including 128 TDM channel support for telephony interfaces such as H.100/H.110 Up to 12 TDM stream support, each with 128 channels per frame Companding selection on a per channel basis in TDM mode Input data port provides an additional input path to the DSP core configurable as either eight channels of I2S or serial data or as seven channels plus a single 20-bit wide syn- chronous parallel data acquisition port Supports receive audio channel data in I2S, left-justified sample pair, or right-justified mode Signal routing unit provides configurable and flexible connections between all DAI components, six serial ports, an input data port, two precision clock generators, three timers, 10 interrupts, six flag inputs, six flag outputs, and 20 SRU I/O pins Serial peripheral interface Master or slave serial boot through SPI Full-duplex operation Master-slave mode multimaster support Open drain outputs Programmable baud rates, clock polarities, and phases 3 Muxed Flag/IRQ lines 1 Muxed Flag/Timer expired line ROM based security features: JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multi- plier/divider ratios JTAG background telemetry for enhanced emulation features IEEE 1149.1 JTAG standard test access port and on-chip emulation Dual voltage: 3.3 V I/O, 1.2 V core Available in 136-ball BGA and 144-lead LQFP packages Lead free packages are also available

TDA4864引脚说明： 8 - 32位和16 - 32位字包装选择可编程等待状态的选择：2至31个CCLK数字音频接口包括6个串行端口，两个前643时钟发生器，输入数据端口， 3可编程定时器和一个信号路由单元串行端口提供：六双串口数据线，在高达50 Mbps的操作/为200兆赫的每个数据行每个人都有一个时钟，帧同步的核心秒，和两个数据可以作为任何一个接收器或发射器对左对齐和I2S样本对支持，最多可同时接收或传送24个频道，每使用两个系列的I2S兼容立体声设备配置可编程方向线；港口的TDM通信接口，包括支持128个电话接口的TDM的渠道，如H.100/H.110支持多达12个的TDM流的支持下，每帧128个频道每个压缩扩展每通道的基础上选择在TDM模式输入数据端口提供了一个额外的输入路径的DSP核心配置为I2S或串行数据或7加一个20位宽的SYN -异步的并行数据采集接口通道或8通道；支持接收通道I2S音频数据，左对齐样本对，或右对齐模式信号路由单元组件之间提供所有戴配置和灵活的连接，6个串行端口，一个输入数据端口，两个精密时钟发生器，3个定时器，10个中断，六旗投入，产出6个旗，20曼谷南南区域股的I / O管脚串行外设接口的硕士或奴隶通过SPI串行启动全双工运作主从模式多主机支持开漏输出可编程波特率，时钟极性和第三期合并调制旗/ IRQ线路1合并调制旗/定时器过期线光盘的防伪特征：JTAG的访问与64位受保护的关键允许内存内存可分配给程序访问控制的限制下对敏感地区有一个代码锁相环/分比率背景遥测的JTAG仿真功能增强的IEEE 1149.1 JTAG标准测试访问端口软件和硬件多钳各种各样和片上仿真双电压：3.3六/输出，可在1.2 V核心136球BGA封装和144引脚LQFP封装无铅封装，也可

The co-channel interference rejection filter for outputting a second input signal by removing co-channel interference from a first input signal; a first post processor for removing interference other than co-channel interference from the second input signal; a second post processor for removing interference other than co-channel interference from the first input signal; and a selection controller for selecting the output of the post processor which has less error by comparing the output of the first post processor with the output of the second post processor.

一种共道干扰消除器及其方法，其中抗共道干扰滤波器从第一输入信号中除去共道干扰并输出第二输入信号，第一后置处理器除去第二输入信号中的非共道干扰，第二后置处理器除去第一输入信号中的非共道干扰，选择控制器比较第一后置处理器和第二后置处理器的输出，从中选择误差较小的后置处理器输出。

An equal cross-section blade was investigated and a finite element model was built parametrically. Geometrical parameters (such as length, width and thickness), material parameters (such as young's modulus and density) and speed of blade were considered as input random variables while the static frequencies and dynamic frequencies were output random variables. Combining the finite element method, response surface method and Monte Carlo method, the statistical properties and cumulative distribution functions of static frequencies and dynamic frequencies were obtained. Probability sensitivities analysis, which combined the slope of the gradient and the width of the scatter range of the random input variables, was applied to quantitatively evaluate the sensitivities of static frequencies and dynamic frequencies with respect to the random variables. The Scatter plots of structural responses with respect to the random input variables were illustrated how to adjust the values of the static frequencies and dynamic frequencies by changing input random variables.

文中以某试验台用汽轮机等直叶片为研究对象，考虑几何参数、材料参数和转速的随机性，通过有限元参数化建模，将确定性有限元方法、响应面方法和Monte-Carlo模拟法相结合，从而获得了叶片静频、动频的统计特性和累积分布函数；同时考虑随机变量的梯度和离散范围对静、动频的影响，通过概率敏感性分析，定量地判断出叶片静、动频对随机输入变量的敏感性；通过绘制叶片静、动频与输入变量的散点图，定量地分析了如何改变随机变量以调整静、动频率的方法。

Based on the return map and the principle of closed vectors, a new method is proposed to extract unstable periodic orbits embedded in chaotic attractors. As examples, the UPOs embedded in chaotic attractors of Logistic, Hénon and Lorenz are extracted respectively by this method. And our results of Skewed Hénon map also be compared with Nusse's. These results suggest that this method is valid for unstable periodic orbits from period one to period infinite of arbitrary dimension chaotic system. The dynamic considerations of spiking and UPO coding for individual neuron and neural system under external periodic and chaotic exciting stimulus also be studied in this dissertation. A lot of spiking phenomena, such as synchronization, period, and chaos appear alternatively with the changing of the stimulus frequency. For the small stimulus frequency the neuron could completely convey the periodic signal in synchronous anti-phase into interspike intervals sequences. For the slow time–scale chaotic input, the output two ISI sequences are reciprocally related to input signals, and their oscillation wave shape in time course can be derived from that of the input signals variation, furthermore, the similar input sequence and order of UPOs, distribution of LES and value of KYD remain in attractors reconstructed from ISI sequences.

发现周期信号在单个神经元传递过程中，随着激励频率的改变，神经元输出的峰峰间期interspike interval时间序列呈现出周期、混沌和准周期的交错变化，特别当外加激励信号频率较低时，周期信号可以通过神经元ISI序列以反相同步的周期运动形式传递下去；同时无论是周期还是混沌激励信号，在神经系统中的传递均与其自身强度和神经元之间的耦合强度的大小密切相关；快变时间尺度的混沌激励信号在耦合的神经系统传递过程中，会造成大量基本信息的丢失；而慢变时间尺度的混沌激励信号在神经系统传递中，它的非线性特征信息，如混沌吸引子、不稳定周期轨道、Lyapunov指数谱和分形维数，会通过系统输出的ISI序列部分地重现出来，如与输入慢变时间尺度的混沌激励信号相比，神经系统输出的ISI序列具有：相似几何形状的混沌吸引子、相近的Lyapunov指数谱和分形维数、局部结构相同的不稳定周期轨道的排列方式。

This high voltage electrostatic precipitation controller has 7 channels of analog input,2 channels of analog output, 12 digital inputs and 16 digital outputs. The analog input includes primary current, secondary current, primary voltage, secondary voltage, etc. Controller uses MAX 187 as the A/D converter, which ensure the sampling speed and the conversion precision in the same time. The processor unit is RCM2250 module. Rabit 2000 processor, a 128K SRAM and a 256K Flash Rom are integrated in RCM2250, which improves the performance of pricipitation controller. MAX504 is used to produce the 4~20mA current output.

模拟量输入采集的信号有升压变压器一次电流、一次电压、二次电流、二次电压等，采用12位逐次比较式A/D转换器MAX187，兼顾采样速率和转换精度；中央处理单元采用以8位嵌入式处理器Rabbit2000为基础的RCM2250模块，外扩128KSRAM和256K Flash ROM，内部资源丰富，提高了控制器的整体性能；模拟量输出采用内带基准源的10位电压输出数模转换器MAX504，实现了标准4～20mA电流信号输出；控制器通过控制算法在相应开关量点上输出可控硅的触发脉冲。

It is shown from the accelerated lifetime test and noise measurement for integrated operational amplifiers that if their failure is caused by the drift of input bias current or input offset current, the drift is strongly correlated with 1/f noise current in these devices, and both are proportional approximately.

摘要寿命试验和噪声测试结果表明，如果集成运算放大器的主要失效模式是输入偏置电流或失调电流随时间的漂移，则这种漂移量与运放的1/f噪声电流具有强相关性，二者近似呈正比关系。

A class of fast-scale bifurcations appearing around the maximum value of the input voltage is discovered for the first time by experiment. Then the influence of the fast-scale bifurcations on the performance of the PFC converters is discussed. Whether the fast-scale bifurcations will appear and how wide the bifurcation region depend on the characteristics of the current loop output. Therefore, the main factors that affect the current loop output are analyzed, including the current loop parameters, inductance, and root-mean-square value of the input voltage.

通过实验，该文首次发现了一类在输入电压最大值附近发生的快时标分岔；详细讨论了快时标分岔对PFC变换器性能的影响；由于电流环输出的特点决定了变换器是否会出现快时标分岔以及分岔区域的大小，该文分析了影响电流环输出的主要因素，包括电流环参数、电感值和输入电压有效值。

CY2000 stable high-current test system or are only a computer-controlled automatic recording systems, real-time monitoring of input current waveform, but also by setting the trigger conditions×transient input current waveform.

CY2000大电流稳升试验测试系统是国内唯一一款计算机控制的自动记录系统，可实时监测输入电流波形，还可按设定的触发条件扑捉瞬态输入电流波形。

Operational Tran conductance lifers and Grounded actorhas become one of the most important methods to implement integrated continuous-time filters. Operational Tran conductance Amplifierscan transfer input voltage into current to output,and control or change output current within large range by an external controlling current of amplifier. Most articles consider OTA as a voltage-mode circuit component and give voltage-to-voltage transfer function of all having been implemented filter circuits,i.e. The input signal and output signal of filter circuits are voltages .

运算跨导集成运算放大器OTA ( Operational Tran conductance Amplifier 以下简称跨导运放)的功能是将输入电压转换为电流输出，并通过外加偏置电流控制运放的工作电流，从而使它的输出电流在较大范围内变化，而在大多数文献中，器件都被作为电压模式元器件使用实现的各种滤波电路都是按传送电压比给出的，即滤波电路输入信号和输出信号均为电压信号。

Fostering the concept of multi-culture firmly and mastering the development of advanced culture correctly are conductive to resisting terrorism, separatism of nationalities and ultraism of religion, which is of great academic theoretical, immediate and profound historical si...

牢固树立多元文化的理念和正确把握先进文化的发展方向，有助于在世界范围内自觉地抵制恐怖主义，民族分裂主义和宗教极端主义。不仅具有重大的学术理论意义，而且也具有重大的现实意义和深远的历史意义。

But if anyone walks in the night, he stumbles, because the light is not in him.

11：10 若在黑夜行走，就必碰跌，因为那光不在他里面。