查询词典 fall to bits

Computer science a bit that is used in an error detection procedure in which a 0 or 1 is added to each group of bits so that it will have either an odd number of 1's or an even number of 1's; e.g., if the parity is odd then any group of bits that arrives with an even number of 1's must contain an error

parity：简介奇偶校验位，在数据存储和传输中，字节中额外增加一个比特位，用来检验错误。它常常是从两个或更多的原始数据中产生一个冗余数据，冗余数据可以从一个原始数据中进行重建。不过，奇偶校验数。。。详情

Computer science an error detection procedure in which a bit (0 or 1) added to each group of bits so that it will have either an odd number of 1's or an even number of 1's; e.g., if the parity is odd then any group of bits that arrives with an even number of 1's must contain an error.

差错检测过程附加在一组二进制数字上的一个二进制数这一位用来使所有数字的和总是一个奇数；或者总是一个偶数。

One of the ways to solve the problem above is actualizing the digital corresponding, transforming the image to the digital signals, wiping off the redundancy outlying of the image quality. Furthermore, on the precondition of ensuring the quality, storaging, recording and transmitting the digital signals is oecumenical, credible and all wool and a yard wide using least bits or bits ratio.

解决这个问题的途径之一，是实现图像通信的数字化，把图像信息转换成数字信号，去除与图像质量无关的冗余信息，并且在保证质量的前提下，用最少量的数码或数码率，实现各类图像的数字存储、数字记录或数字传输，达到优质、可靠、经济的要求。

Its default address size is 64 bits and its default operand size is 32 bits.

它的默认地址大小是64位，默认操作数大小是32位。

BER. The percentage of received bits in error compared to the total number of bits received.

BER。接收到错误比特数与所接收到的比特总数之比。

Upgrade 2 bits Pre-fetch of DDR DRAM to 4 bits Pre-fetch, this is DDR2 SDRAM. In this paper, we propose the method and standard of PCB layout of DDR2 SDRAM.

将DDR SDRAM的2位元预取(2 bits Pre-fetch)技术升级为4位元预取(4 bits Pre-fetch)技术，提高SDRAM资料存取的容量；这就是所谓的第二代双倍资料率同步动态随机记忆体：DDR2 SDRAM。

Furthermore, instead of storing actual wordID's, we store each wordID as a relative difference from the minimum wordID that falls into the barrel the wordID is in. This way, we can use just 24 bits for the wordID's in the unsorted barrels, leaving 8 bits for the hit list length.

此外，而不是存储实际wordID的，我们将存储每个wordID作为一个相对差的最低wordID是落入每桶60英寸wordID是这样，我们可以只使用24位的wordID的在未经桶，使8位为暗杀名单的长度。

RL That was 64 bits, so the 69 bits of security for SHA-1 is not that far away.

当时它是64位系统，因此，69位的SHA-1安全性的破解也并非遥遥无期。

The ADC is pipelined, including a single-input/difference-output sample/hold circuit and nine stage subcircuits. The preceding eight stages are 1.5bits/stage, and the last stage consists of two comparators. Every input sample is converted into 18 bits binary signals, and these binary signals are converted into 10 bits binary signals through digital correction circuit.

模数转换电路采用流水线式的结构，包括具有单端输入/差动输出功能的采样保持电路和九级的子电路，前八级子电路使用1.5位/级的结构，最后一级使用两个比较器实现，每个输入值被转换为18位的二进制代码，通过数字纠正技术最终实现10位的输出，按照前端电路的应用要求，这个模数转换器实现1.33MHz的采样速率。

Bits that are cleared indicated a missing piece, and set bits indicate a valid and available piece.

已清除的位则指出缺少的片断，通过一个有效可用的片断来设置位。

The second is to cut a mere 100 calories from your diet , which is the equivalent of a tablespoon of butter.

第二个就是从你的饮食中减少一百卡路里，只是相当于一大汤匙的黄油。

This is where the Rorschach test comes in.

现在，罗氏测试就出现了。