查询词典 combinational logic

A model is proposed in this paper to deal with the signals which drive the combinational logic gates working at nonlinear region. The frequency analysis method is able to provide higher accuracy, while significantly speeding up simulations.

为了解决组合逻辑电路有时会工作在信号非线性区的问题，提出一种数学模型来精确描述瞬时错误在组合逻辑电路中传播过程。

Evolvable algorithms are applied to functional digital combinational logic circuits with the structure of ClassicEPGlO chip of Altera Co. and the detailed analyses of typical examples are also given.

结合Altera公司ClassicEP610芯片的结构，研究了将演化算法应用于函数级数字组合逻辑电路的硬件演化，并且对典型实例进行了详细分析。

This design which is based on the WindowsXp platform, using Graphic editor and text editor of MAX+PLUS II, to design Linear block code through VHDL and Combinational logic. both of these realization are simulated.

本设计基于windows xp平台，采用MAX + Plus II软件中的图形编辑模块和文本编辑模块，运用VHDL对线性分组编码器的编码功能，进行组合逻辑电路设计以及VHDL设计，并对两种设计进行波形仿真。

By adding a single bit to a data register (212) of each of a plurality of TAP controllers (102, 106), along with straightforward combinational logic, the plurality of TAP controllers can be accessed without the need for additional chip pins, and without the need for additional TAP controllers.

通过向多个TAP控制器(102，106)的每一TAP控制器的数据寄存器(212)以及直接组合胶合逻辑添加单个位，能够访问所述多个TAP控制器，而无需额外的芯片管脚，并且无需额外的TAP控制器。

Based on the analyzing of finite field multiply operation, Matlab was used to simplify the sections which were complex and resource-consumed. As a result, a simple form of combinational logic was obtained. And bit-parallel multipliers under nature or dual basis were designed separately in finite-field with VHDL language.

在分析有限域乘法运算法则的基础上，用Matlab简化其复杂而消耗资源的部分，得到形式简单的组合逻辑，并用VHDL语言分别设计了有限域GF(2m)中自然基和对偶基下比特并行乘法器。

Multi-output combinational logic functions are located on the Karnaugh map and the common parts of each function overlap on this map, which makes it easier to find congener common miniterms and merge them.

该化简法要求用一张卡诺图表示多输出逻辑函数，使得它们的共享部分在几何上相互重叠，为辨识同类共享最小项和合并提供了方便。

Combinational Logic design which based on the theory of Linear block code is the circuit map of Linear block code using AND-gate, OR-gate, Flip-flop and so on. VHDL design is the hardware description of the circuit map to make linear block code into realization.

组合逻辑电路设计，是根据线性分组编码理论，利用与非门、触发器等逻辑器件搭建起来的电路原理图；VHDL设计，是将线性分组编码理论通过用VHDL描述，实现其编码功能。

Combinational Logic design which based on the theory of Linear block code is the circuit mapof Linear block code using AND-gate, OR-gate, Flip-flop and so on. VHDL design is the hardware description of the circuit map to make linear block code into realization.

组合逻辑电路设计，是根据线性分组编码理论，利用与非门、触发器等逻辑器件搭建起来的电路原理图；VHDL设计，是将线性分组编码理论通过用VHDL描述，实现其编码功能。

The NOT, OR and XOR gate of combinational logic were replaced by the polyphenylene based molecular device whileTour-type molecular wire constitute the framework in the molecular circuit accounting for the geometry and steric constraints imposed by the bonding and shapes of the organic molecules.

为了在分子电路水平实现减法运算，按照固态电子学组合逻辑原理，提出了一种基于聚亚苯基分子器件的二进制减法器逻辑电路的设计。

Unlike previous methods which rely on look-up tables to implement the SubBytes, we use the combinational logic which is only based on arithmetic operations in the finite field GF (2^8) with 3 substages.

文章在研究有限域GF(2^8)与其复合域GF(2^4^2变换的基础上，采用组合逻辑替代RAM查表的方法实现SubBytes变换，并在其内部实现了三级流水线。

The teacher likes the honeymouthed little girl very much.

老师很喜欢这个嘴甜的小姑娘。

Mr. Notker Bien's interests are traveling, spending quality time with the family and long-distance-running.

诺特卡·柏恩先生热爱旅游，长跑，以及和家人一起共度美好时光。