查询词典 buffer arm

Introduce some methods to realize high-speed buffer memory.

介绍了几种实现高速缓存的方法，以及利用 Intel8237制作一个 DMA 控制器，详细介绍了 DMA 传输的原理和条件，解决了 DMA 控制器和外部接口电路的设计问题，并且给出了 DMA 控制器的初始化程序。

The decoder module can decode the picture received from the input high-speed buffer module.

解码器模块可以对从输入高速缓存器中接收的画面进行解码。

As a result, the development of networks is restricted severely. This paper presents a tri-stage memory array architecture to solve the problem, which can accomplish the arbitrary high-speed packet buffer theoretically.

提出一种新型的三级存储阵列结构可以成功解决数据包存储器的容量和带宽问题，理论上可以实现任意高速数据包的缓存。

One element used during processing operations is a high-speed buffer memory that's both faster and more expensive per character stored than primary storage.

它的速度比主存快，但每存储位的成本比主存高。

But by high-speed static RAM buffer composition, structure more complex, in the CPU die area can not be the case too, L1 cache capacity level can not be done too.

不过高速缓冲存储器均由静态RAM组成，结构较复杂，在CPU管芯面积不能太大的情况下，L1级高速缓存的容量不可能做得太大。

This paper presents synchronous FIFO integrated in FPGA which can achieve the function of high-speed buffer and bus synchronous data transmission by high-speed reading-writing operation of the FIFO.

本文提出一种基于FPGA片上集成的高速FIFO实现采集数据的高速缓存并通过对高速FIFO的读写操作实现总线同步数据传输，提高数据的传输速率。

The local monitor module was in charge of monitoring the data changes happened on local host and saving them into high-speed buffer disks.

通过本地监控模块监控数据变化，并将其传输到海量高速缓存中暂存。

But by high-speed static RAM buffer composition, structure more complex, in the CPU die area can not be the case too, L1 cache capacity level can not do too much, L1 cache capacity is generally KB .

不过高速缓冲存储器均由静态RAM组成，结构较复杂，在CPU管芯面积不能太大的情况下，L1级高速缓存的容量不可能做得太大，L1缓存的容量单位一般为KB。

Use Cygnal Inc C8051F120 singlechip to control start-up and stop of system, permission of data acquisition, data transmission etc. Use Altera Inc Cyclone II series EP2C8Q208C7 chip to control buffer of high-speed data and sample of storage etc.

采用Cygnal公司的C8051F120单片机控制系统的启动、停止，数据采集的允许，数据传输等；采用Altera公司CycloneⅡ系列的EP2C8Q208C7芯片控制高速数据的缓存和存储点数等。

The dual channels AD converter AD9238-40 was used as input stage,two asynchronous FIFOs on-chip were used as high-speed buffer memory,and the sampling and adaptive filtering was controlled by FPGA.

仿真结果表明：该方案既能降低系统的成本，又能有效降低高频可能引起的干扰，对于高速实时电路处理具有一定的参考意义。

We have something to do in the new stage.

在这段崭新的时期中，我们有一些要做的。

The difference between tourism decision-making under uncertainty and risky tourism decision-making is indistinctive.

其中不确定性旅游决策和风险旅游决策的界线比较模糊，两者的区分是相对的。