查询词典 associative array processor

In the light of the underlying ideas behind smart antenna and multiuser detection, a novel multi-user detector based on the parallel array constant modulus algorithm processor , and on the adaptive space-time interference cancellation algorithm, is proposed.

将智能天线与多用户检测的思想相结合，提出了以时空盲估计和时空干扰对消为基础的多用户检测算法，该算法充分利用了信号的时域恒模特性和信号时空特征。

By applying programmable device, like Field Programmable Gate Array or Digital Signal Processor etc, more signal processing methods can be carried on to get detail information about target signals.

利用FPGA或DSP等可编程器件对所截获低速率信号进行处理，得到目标信号的详细参数。

They can solve the problems as follows: 1 To combine the systolic array processor with the delay register arrays, they allow serial data input to save the pin counts but perform parallel processing.

在原型阵列的基础上进行结构改进，本文相应完成了三种实用化FSBM脉动阵列的设计。

In this strategy, IPM was used to generate 3-phase power for the AC motor; the WFG unit of 80C196MC was used to generate the control signal of SPWM, A/D convertor unit to complete the sampling of current, and Event Processor Array to complete the detection of speed.

该方案利用受控于单片机的智能功率模块产生电机的三相电压；利用80C196MC单片机中的WFG产生SPWM信号，芯片内的A/D转换器实现电流采样，事件处理器阵列实现了转速检测。

In this thesis, we improve the existing rendering algorithm and propose a power-aware system architecture including three key modules: dynamic task dispatcher, dynamic task scheduler, and 2-stage precision-aware processor array.

在本论文中，我们改良了既有的绘图演算法，并且提出了具备功率感知功能的系统架构。其中包括三个关键模组：动态资料流分派器，动态资料流排程器，以及具备精确度感知的处理器阵列。

Each of the subband signals is then fed into its corresponding subband array processor, of which the outputs are combined by the synthesis filter and recovered into wideband signal.

宽带接收信号经分析滤波器组分成若干子带信号，每个子带信号经各自的子带阵列处理器处理后由综合滤波器恢复成宽带信号。

The BT headset has powerful digital signal processor with 120 MIPS of digital processing power, supports dual microphone array, four-button operation, multiple device pairing, with up to 7 hours of talk time and 100 hours of standby time.

BT的耳机具有强大的数字信号处理器的120 MIPS的数字处理能力，支持双麦克风阵列，四个按钮操作，多种设备配对，与高达7小时的通话时间和100小时的待机时间。

Based on a new modified Wallace multiplier structure, named bi-forked Wallace multiplier structure, this paper presents the design of a highly re-configurable Multiplier for VLIW multimedia-processor. We found a reusable design method to extend multiplier with full adder array. The Structure can enable 32/16/8 bit operands, and has been optimized for speed and area.

在VLIW多媒体芯片的设计过程中，针对传统乘法器与加法器的不足，提出了一种新的分叉华莱氏树结构的乘法器模型，采用可重用的模块化设计思想，通过重用一位全加器阵列对乘法器进行扩展，处理器可以在一个乘法器单元内部同时支持多个32/16/8位的乘法运算，同时使乘法单元的速度和面积均得以优化。

Based on the idea of mapping the loops onto the reconfigurable array can improve the performance, this paper presents a novel reconfigurable processor which can execute the loop automatically with loop controller.

基于将循环映射到可重构阵列上能提高其执行速度的思想，提出了了一种能够适合循环任务的可重构处理器。

And when the array transmits back to the cell-phone user, the processor sends an out-of-phase signal to one of the antennas, generating a radio beam that runs from north to south.

当阵列发射讯号给行动电话用户时，处理器会传送一个异相的讯号到其中一个天线，产生由北往南的无线电波束。

The statistical analysis of this large set of mutations has led us to propose a diagnostic strategy that should help with the molecular work-up of optic neuropathies.

这一大系列基因突变的统计学分析引导我们提出一个诊断策略，可以帮助我们对视神经病变进行分子学的诊断检查。

The results show that the pipe grouting changes the mechanical parameters of surrounding rocks to achieve the security of engineering objectives by reinforcing surrounding rocks and bolcking the water.

研究表明：小导管注浆一方面改变了围岩的力学参数，另一方面利用浆液的固结特性可以实现堵水和加固围岩的工程目标，使隧道在开挖过程中的安全得到保障。