逻辑块

词组短语

logical block

与逻辑块相关的网络例句 [注：此内容来源于网络，仅供参考]

A contiguously addressed range of logical blocks on a physical media that is identifiable by an operating system via the partition's type and subtype fields.

分区是能够被操作系统通过分区的类型和子类型域而识别出的物理介质上的一个连续编址的逻辑块区间。

SCSI disk commands addressed to RAID arrays, are actually using virtual block addresses in their logical block address fields.

也就是说发给RAID阵列的SCSI磁盘命令中，实际上是在逻辑块地址字段使用虚拟块地址。

The method includes establishing one reverse mapping list comprising list items; reading the mapping data recorded in the data block state list item area to the list items during system initialization; checking reverse mapping list and finding the data block in Flash memory during reading some logic block; and writing the updated data into the empty data area of one new data block, writing the mapping data between the new logic block and the new data block into the state list item area and updating the mapping data of the corresponding list item in the reverse mapping list during writing some logic blcok.

包括：建立一个由表项组成的反向映射表，一个表项对应一个逻辑块；在系统初始化过程中，将数据块状态表项区中记录的映射信息，按逻辑块号与表项间的对应关系读取到各表项中；读取某逻辑块时，以其逻辑块号作为表项索引查找反向映射表，定位到表项，根据表项中记录的映射信息，在Flash存储器件中查找到数据块；写入某逻辑块时，将更新数据写入一新数据块的空白数据区中和将该逻辑块与新数据块间的映射信息写入状态表项区中，同时更新反向映射表相应表项的映射信息。

Mapping from logical to physical in a file of maximum size of 256K words and block size of 512 words. We need only 1 block for index table.

为了从逻辑映射到实际的文件系统，一个256K字的文件，块为512字，我们只需一个块作为索引表

The algorithm combines the simulated annealing algorithm with ratio-cut method to ascertain the level of the multi-level multi-way partitioning. Considering the number of cut lines while partitions CLB into cluster, it achieves a better partition result and improve the usage in HFPGA, then optimize the FPGA performance.

该算法将模拟退火算法与ratio-cut思想结合，确定多层多划分的规模后，采用数据结构进行多分优化，在将可配置逻辑块(configurable logic block， CLB)划分到各个簇的时候考虑割线数的目标函数，实现了更好的划分结果，提高了FPGA芯片的利用率，优化了整个芯片的性能。

The measured object can be found within a few milliseconds in the raster-scan image. 4 . Two lines delay for the processed image is implemented using two 128×8 shift registers with the configurable logic block in FPGA. A new fully pipelined bit parallel hardware architecture for Sobel edge detection is implemented with FPGA. Furthermore, it takes no more than 2ms to complete the edge detection of an image with 128×128 pixels.

视觉检测信号的前端处理技术 1、系统地分析了视觉检测算法层次性特点和计算特点，提出了提高视觉检测信号处理速度的基本方案：采用前端处理系统，自动识别被测物体在获取图像中的位置，并将真正有用的被测物体的边缘坐标值，提供给计算机，作进一步的高精度处理； 2、系统研究了实时图像硬件处理的设计基本方法，提出了基于FPGA的视觉检测信号的低级处理算法硬件实现模块化模型； 3、提出了一种新的基于FPGA的模板匹配并行模块化结构，解决了二维图像处理高带宽要求，在几毫秒内就可以在按扫描顺序输入图像中找到检测目标物体的位置； 4、采用FPGA内部的可配置逻辑块实现了128×8移位寄存器的设计，解决了大容量移位寄存器与FPGA内部寄存器数量之间的矛盾，实现了两行图像的延迟。

When this block is executed, there will be two events added to the nonblocking assign update queue.

4：当在同一个 always 块里面既为组合逻辑又为时序逻辑建模，使用&非阻塞赋值&。

The logic block mapping speeding method in Flash file system can raise the data search speed.

本发明涉及一种在Flash文件系统中加快逻辑块映射速度的方法，可提高查找数据块的速度。

All-Flash website and the production of similar html website, prior should be painted on paper restructuring plan, including : Terms of the theme, with what kind of elements, which elements need to repeat them use elements of the link between how elements of campaign what style of music, the entire site can be divided into several logic blocks, each logic block the link between how and whether you intend to use Flash construct the station or just doing their part of the preliminary site etc., should be considered within the scope.

制作全Flash网站和制作html网站类似，事先应先在纸上画出结构关系图，包括：网站的主题、要用什么样的元素、哪些元素需要重复使用、元素之间的联系、元素如何运动、用什么风格的音乐、整个网站可以分成几个逻辑块、各个逻辑块间的联系如何、以及你是否打算用Flash建构全站或是只用其做网站的前期部分等等，都应在考虑范围之内。

The core of test theory for a new generation of test is the combination of psychometrics and cognitive psychology, which is the key idea of the article .The article supposes there are four factors underlying response difficulty of Raven's Standard Progressive Matrices: figure complexity, figure format, transformation dimension, location factor. The hypothesis is tested by linear logistic latent trait model and proved to be valid.

本文在以认知和测量相结合为核心的新一代测验理论的指导下，从瑞文标准推理测验项目刺激特征的角度，对项目认知难度的影响因素进行了认知分析，提取出四个因素：图块繁简度、图块布局、变化维度、题序因子，结合线性逻辑斯谛克潜在特质模型对这四个因素进行了检验，证明提取出的四个因素是有效的。

与逻辑块相关的网络解释 [注：此内容来源于网络，仅供参考]

BLA BinaryLogicalAssociation：二进制逻辑联想

BL BritishLibrary 英国国家图书馆 | BLA BinaryLogicalAssociation 二进制逻辑联想 | BLA BlockingAcknowledgement 组成块确认

blocks：块

于是,逻辑行形成了"块"(blocks). 如果在两个逻辑行之前有着同样的缩进(indentation),同时在这两行中间没有比它们的缩进更小的逻辑行出现,那么这两行就组成一个块. 注意:缩进只能由空格(space)组成,不能是制表符(tab).

functional block：功能块

每个功能块(functional block)包括16个数据流处理器,结合成4个纹理单元和二级高速缓存. 图2显示了有8个功能块的高端GeForce 8800 GTX的逻辑功能块图. GeForce 8800 GTS使用6个功能块,布局也类似.

granularity：间隔尺寸

音视频块的间隔尺寸(Granularity) 数据块的间隔尺寸是一个AVI文件的逻辑块大小. 它用于写和读音视频数据块. 当向磁盘写音视频数据时, AVICap 将在每个数据块中加入一个必须的填充块(filler chunks (RIFF "JUNK" chunks)) 去填充满该数据块.

logic element：逻辑单元

其中,逻辑阵列是由多个逻辑阵列块(LAB)组成的,而每个逻辑阵列块(LAB)又包含8个逻辑单元(logic element),在每行、列互连通道的两端都有输入/输出单元(IOE).

logical circuit：逻辑电

logical channel control block | 逻辑通道控制块 | logical choice | 逻辑选择 | logical circuit | 逻辑电

logical block diagram,LBD：逻辑方块图

"逻辑块定址","logical block addressing,LBA" | "逻辑方块图","logical block diagram,LBD" | "逻辑块号码","logical block number,LBN"

logically equivalent：逻辑等价

"逻辑相连块","logically contiguous block" | "逻辑等价","logically equivalent" | "逻辑被动自对偶","logically passive self-dual,LPSD"

Stepwise Refinement：逐步求精

它的基本组成单元是一些逻辑块,而这些块又能嵌套任意数量子块.通常, 每一个逻辑块都承担一部分工作任务, PL/SQL 这种将问题分而治之(divide-and-conquer)的方法称为逐 步求精(stepwise refinement).块能够让我们把逻辑相关的声明和语句组织起来,

GLIS GenericLogicBlock：普通逻辑块

GLY GenericLoadSegment 通用装载字段 | GLIS GenericLogicBlock 普通逻辑块 | GRY GenericRunTime 一般运行时间