输出管

DISPLAY OUTPUTS The most common output device is the monitor,a cathode-ray tubethat is basically a television tube adapted to present text,data,or images generated by computers.

显示输出最常用的输出设备要算监视器了，它是与电视机显像管基本相同的阴极射线管，经改制以适应显示由计算机产生的文本、数据或图像。

A novel hybrid diode-clamp cascade multilevel converter is presented in this paper. The new concept of the converter is based on connection of multiple diode-clamp converter modules with different dc bus voltages. Normally, the voltage blocking capability of faster devices such as IGBT and the switching speed of high voltage devices like GTO are found to be limited.

该文在研究传统的级联多电平、传统混合级联多电平以及二级管钳位级联多电平变换器的基础上提出了一种新型的混合二极管钳位级联多电平变换器，这种新型变换器是将具有不同直流母线电压的多个二极管钳位多电平变换器进行级联，输出电压是将这些变换器的输出电压进行矢量相加而合成的。

The Engineer shall measure the RPM of the Main Engine, draft, compression pressure in the cylinder, maximum pressure in the cylinder, load indicator, exhaust temperature, scavenging pressure and temperature, rpm of the supercharger, etc. to grasp the operating condition of the Main Engine, and also calculate

轮机员须测取主机转速、汽缸内的压缩压力、最大爆发压力、负荷指示、排烟温度、扫气压力和温度、透平转速等，获得主机操作工况，同时计算主机输出功率、燃油消耗率、汽缸油消耗率等，根据计算准备&主机输出功率报告&，这些必须经过大管轮的检查和验证，并递交轮机长。

MAX1999EEI Pinout: 8- to 32-bit and 16- to 32-bit word packing options Programmable wait state options: 2 to 31 CCLK Digital audio interface includes six serial ports, two pre- cision clock generators, an input data port, three programmable timers and a signal routing unit Serial ports provide: Six dual data line serial ports that operate at up to 50 Mbits/s for a 200 MHz core on each data line each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair Left-justified sample pair and I2S support, programmable direction for up to 24 simultaneous receive or transmit channels using two I2S compatible stereo devices per serial port TDM support for telecommunications interfaces including 128 TDM channel support for telephony interfaces such as H.100/H.110 Up to 12 TDM stream support, each with 128 channels per frame Companding selection on a per channel basis in TDM mode Input data port provides an additional input path to the DSP core configurable as either eight channels of I2S or serial data or as seven channels plus a single 20-bit wide syn- chronous parallel data acquisition port Supports receive audio channel data in I2S, left-justified sample pair, or right-justified mode Signal routing unit provides configurable and flexible connections between all DAI components, six serial ports, an input data port, two precision clock generators, three timers, 10 interrupts, six flag inputs, six flag outputs, and 20 SRU I/O pins Serial peripheral interface Master or slave serial boot through SPI Full-duplex operation Master-slave mode multimaster support Open drain outputs Programmable baud rates, clock polarities, and phases 3 Muxed Flag/IRQ lines 1 Muxed Flag/Timer expired line ROM based security features: JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multi- plier/divider ratios JTAG background telemetry for enhanced emulation features IEEE 1149.1 JTAG standard test access port and on-chip emulation Dual voltage: 3.3 V I/O, 1.2 V core Available in 136-ball BGA and 144-lead LQFP packages Lead free packages are also available

MAX1999EEI引脚说明： 8 - 32位和16 - 32位字包装选择可编程等待状态的选择：2至31个CCLK数字音频接口包括6个串行端口，两个前643时钟发生器，输入数据端口， 3可编程定时器和一个信号路由单元串行端口提供：六双串口数据线，在高达50 Mbps的操作/为200兆赫的每个数据行每个人都有一个时钟，帧同步的核心秒，和两个数据可以作为任何一个接收器或发射器对左对齐和I2S配对样本的支持下，最多可同时接收或传送24个频道，每使用两个系列的I2S兼容立体声设备配置可编程方向线；港口的TDM通信接口，包括支持128个电话接口的TDM的渠道，如H.100/H.110支持多达12个的TDM流的支持下，每帧128个频道每个压缩扩展每通道的基础上选择在TDM模式输入数据端口提供了一个额外的输入路径的DSP核心配置为I2S或串行数据或7加一个20位宽的SYN -异步的并行数据采集接口通道或8通道；支持接收通道I2S音频数据，左对齐样本对，或右对齐模式信号路由单元组件之间提供所有戴配置和灵活的连接，6个串行端口，一个输入数据端口，两个精密时钟发生器，3个定时器，10个中断，六旗投入，产出6个旗，20曼谷南南区域股的I / O管脚串行外设接口的硕士或奴隶通过SPI串行启动全双工运作主从模式多主机支持开漏输出可编程波特率，时钟极性和第三期合并调制旗/ IRQ线路1合并调制旗/定时器过期线光盘的防伪特征：JTAG的访问与64位受保护的关键允许内存内存可分配给程序访问控制的限制下对敏感地区有一个代码锁相环/遥测分比率为背景的JTAG仿真功能增强的IEEE 1149.1 JTAG标准测试访问端口的软件和硬件多钳各种各样和片上仿真双电压：3.3六/输出，可在1.2 V核心136球BGA封装和144引脚LQFP封装无铅封装，也可

TDA4864 Pinout: 8- to 32-bit and 16- to 32-bit word packing options Programmable wait state options: 2 to 31 CCLK Digital audio interface includes six serial ports, two pre- cision clock generators, an input data port, three programmable timers and a signal routing unit Serial ports provide: Six dual data line serial ports that operate at up to 50 Mbits/s for a 200 MHz core on each data line each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair Left-justified sample pair and I2S support, programmable direction for up to 24 simultaneous receive or transmit channels using two I2S compatible stereo devices per serial port TDM support for telecommunications interfaces including 128 TDM channel support for telephony interfaces such as H.100/H.110 Up to 12 TDM stream support, each with 128 channels per frame Companding selection on a per channel basis in TDM mode Input data port provides an additional input path to the DSP core configurable as either eight channels of I2S or serial data or as seven channels plus a single 20-bit wide syn- chronous parallel data acquisition port Supports receive audio channel data in I2S, left-justified sample pair, or right-justified mode Signal routing unit provides configurable and flexible connections between all DAI components, six serial ports, an input data port, two precision clock generators, three timers, 10 interrupts, six flag inputs, six flag outputs, and 20 SRU I/O pins Serial peripheral interface Master or slave serial boot through SPI Full-duplex operation Master-slave mode multimaster support Open drain outputs Programmable baud rates, clock polarities, and phases 3 Muxed Flag/IRQ lines 1 Muxed Flag/Timer expired line ROM based security features: JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multi- plier/divider ratios JTAG background telemetry for enhanced emulation features IEEE 1149.1 JTAG standard test access port and on-chip emulation Dual voltage: 3.3 V I/O, 1.2 V core Available in 136-ball BGA and 144-lead LQFP packages Lead free packages are also available

TDA4864引脚说明： 8 - 32位和16 - 32位字包装选择可编程等待状态的选择：2至31个CCLK数字音频接口包括6个串行端口，两个前643时钟发生器，输入数据端口， 3可编程定时器和一个信号路由单元串行端口提供：六双串口数据线，在高达50 Mbps的操作/为200兆赫的每个数据行每个人都有一个时钟，帧同步的核心秒，和两个数据可以作为任何一个接收器或发射器对左对齐和I2S样本对支持，最多可同时接收或传送24个频道，每使用两个系列的I2S兼容立体声设备配置可编程方向线；港口的TDM通信接口，包括支持128个电话接口的TDM的渠道，如H.100/H.110支持多达12个的TDM流的支持下，每帧128个频道每个压缩扩展每通道的基础上选择在TDM模式输入数据端口提供了一个额外的输入路径的DSP核心配置为I2S或串行数据或7加一个20位宽的SYN -异步的并行数据采集接口通道或8通道；支持接收通道I2S音频数据，左对齐样本对，或右对齐模式信号路由单元组件之间提供所有戴配置和灵活的连接，6个串行端口，一个输入数据端口，两个精密时钟发生器，3个定时器，10个中断，六旗投入，产出6个旗，20曼谷南南区域股的I / O管脚串行外设接口的硕士或奴隶通过SPI串行启动全双工运作主从模式多主机支持开漏输出可编程波特率，时钟极性和第三期合并调制旗/ IRQ线路1合并调制旗/定时器过期线光盘的防伪特征：JTAG的访问与64位受保护的关键允许内存内存可分配给程序访问控制的限制下对敏感地区有一个代码锁相环/分比率背景遥测的JTAG仿真功能增强的IEEE 1149.1 JTAG标准测试访问端口软件和硬件多钳各种各样和片上仿真双电压：3.3六/输出，可在1.2 V核心136球BGA封装和144引脚LQFP封装无铅封装，也可

And the theoretical analyses of this paper show that the new type of gyrotron structure introduced by the author is very advantageous of the stable-frequency output and improving single-mode operation stability, and the efficiency and the output power of the tube can be enhanced due to the effect of the feedback.

理论分析表明，本文所提出的新型回旋管结构极有利于稳频输出和提高单模工作的稳定性；由于反馈的作用，同时亦可提高器件的效率和输出功率。

This design use temperature sense organ to collect environment temperature, change the simulate signal into digital signal.

设计中利用高精度可达0.1的温度传感器AD590采样环境温度，将温度传感器输出的模拟信号经A/D转换器转换为数字信号，再经单片机加工处理，转换为八段显示码，由接口电路输出，驱动数码显示管。

This experiment counts based on the direct digital frequencysynthesis the basic principle, fully II and hardware LT - IV testedthe box using ALtera Corporation's FPGA chip FLEX10 in softwareMaxplus in the platform to complete the DDS system design, hasdesigned a frequency and the phase may control has the sine and thecosine output direct numeral frequency synthesizer, was allowedto control and to observe the profile through the downloading boardand the Oscilloscope , completed in the enhancement request hascontrolled the frequency and the phase through the downloading boardon pressed key, as well as many kinds of profiles, includingsquare-wave, saw-tooth wave, triangle wave and cosine wave choiceoutput, In addition on digital tube dynamic demonstration productionprofile frequency, and produces the tbl document from the simulationprofile, simultaneously draws the profile using the matlab higherorder language.

帮忙翻译一下，谢谢本实验基于直接数字频率合成计的基本原理，充分利用ALtera公司的FPGA芯片FLEX10在软件MaxplusⅡ和硬件LT—IV实验箱的平台上完成了DDS系统的设计，设计了一个频率和相位均可控制的具有正弦和余弦输出的直接数字频率合成器，通过下载板和示波器可以控制和观察波形，在提高要求中完成了通过下载板上的按键来控制频率和相位，以及多种波形，包括方波、锯齿波、三角波和余弦波的选择输出，此外在数码管上动态显示生成的波形频率，并且从仿真波形中生成tbl文件，同时利用matlab高级语言画出波形。

This experiment counts based on the direct digital oscilloscope frequencysynthesis the basic principle, fully II and hardware LT - IV testedthe box using ALtera Corporation's FPGA chip FLEX10 in softwareMaxplus in the platform to complete the DDS system design, hasdesigned a frequency and the phase may control has the sine and thecosine output direct numeral frequency synthesizer, was allowedto control and to observe the profile through the downloading boardand the oscilloscope, completed in the enhancement request hascontrolled the frequency and the phase through the downloading boardon pressed key, as well as many kinds of profiles, includingsquare-wave, saw-tooth wave, triangle wave and cosine wave choiceoutput, In addition on digital oscilloscope tube dynamic demonstration productionprofile frequency, and produces the tbl document from the simulationprofile, simultaneously draws the profile using the matlab higherorder language.

帮忙翻译一下，谢谢本实验基于直接数字频率合成计的基本原理，充分利用ALtera公司的FPGA芯片FLEX10在软件MaxplusⅡ和硬件LT—IV实验箱的平台上完成了DDS系统的设计，设计了一个频率和相位均可控制的具有正弦和余弦输出的直接数字频率合成器，通过下载板和示波器可以控制和观察波形，在提高要求中完成了通过下载板上的按键来控制频率和相位，以及多种波形，包括方波、锯齿波、三角波和余弦波的选择输出，此外在数码管上动态显示生成的波形频率，并且从仿真波形中生成tbl文件，同时利用matlab高级语言画出波形。

To complete the DDS system design, hasdesigned a frequency and the phase may control has the sine and thecosine output direct numeral frequency synthesizer, was allowedto control and to observe the profile through the downloading boardand the oscilloscope, completed in the enhancement request hascontrolled the frequency and the phase through the downloading boardon pressed key, as well as many kinds of profiles, includingsquare-wave, saw-tooth wave, triangle wave and cosine wave choiceoutput, In addition on digital tube dynamic demonstration productionprofile frequency, and produces the tbl document from the simulationprofile, simultaneously draws the profile using the matlab higherorder language.

本实验基于直接数字频率合成计的基本原理，充分利用ALtera公司的FPGA芯片FLEX10在软件MaxplusⅡ和硬件LT—IV实验箱的平台上完成了DDS系统的设计，设计了一个频率和相位均可控制的具有正弦和余弦输出的直接数字频率合成器，通过下载板和示波器可以控制和观察波形，在提高要求中完成了通过下载板上的按键来控制频率和相位，以及多种波形，包括方波、锯齿波、三角波和余弦波的选择输出，此外在数码管上动态显示生成的波形频率，并且从仿真波形中生成tbl文件，同时利用matlab高级语言画出波形。

Since historical times,England ,where the early inhabitants were Celts, has been conquered three times .

从有历史以来，英国，在此地早期居住的是凯尔特人，已经被征服了三次。

Bluetooth OBEX File Transfer Enables the sending and receiving of files on your phone via Bluetooth.

蓝牙OBEX文件移动允许经过蓝牙传送和接受文件。。。。