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In the above examples the address offset from the base register was always an immediate value.

在以上例子中,基址寄存器的地址偏移一直是一个立即数。

The physical address is formed by adding the 16 or 32 bit offset to the base address in the shadow register.

物理地址将由屏蔽寄存器的基地址加上 16 位或者 32 位的偏移地址来形成。

To derive a linear address, a segment register's segment base is added to the segment offset.

为了获得线性地址,要将段寄存器的段基加上段偏移量。

And it is not possible to take the address of a register variable (a topic covered in Chapter 5), regardless of whether the variable is actually placed in a register.

另外,无论寄体器变量实际上是不是存放在寄存器中,它的地址都是不能访问的(有关这一点更详细的信息,我们将在第5章中讨论)。

In this advanced architecture of QC-LDPC codes encoder, the RAM is advisably used to store the parity-check bits and the pointers are introduced as the addresses of the RAM instead of shift registers used for storing the generator of H. Thus, the encoding; process can be achieved by reading and writing on RAM and the parity-cheek bits can be output serially.

采用RAM存储校验位,并引入指针来指示RAM的地址方法,从而取代传统编码架构中的移位寄存器,使编码过程通过对RAM的读写操作实现,校验位序列也通过对RAM的读操作串行输出。

To get rid of these we allocate registers for those variables too.

为了去除这些,我们也为这些变量分配寄存器。

This algorithm is more efficient in solving register allocation problem than clique partitioning algorithm.

该算法在解决寄存器分配问题上比常采用的团划分算法更有效。

This paper defines j-dual automorphism and anti- automorphism of de Bruijn Good graph Gn over F2+vF2 ring.

文章定义了F2+vF2环上的de Bruijn Good图Gn的j对偶自同构及反自同构,并给出了在F2+vF2环上移位寄存器非奇异的充要条件,以及非奇异反馈函数与其自同构函数的表达式。

A processor is composed of two functional units—a control unit and an arithmetic/logic unit—and a set of special workspaces called registers.

一个处理器由两个功能单元----控制单元和计算或逻辑单元,以及一个叫做寄存器的特殊工作空间组成。

The processor contains a clock, an instruction control unit, an arithmetic and logic unit, and

处理器由时钟、指令控制器、算术逻辑运算单元和一些。。寄存器组成,包括指令计数器、指

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