查询词典 programmable function key

MAX1999EEI Pinout: 8- to 32-bit and 16- to 32-bit word packing options Programmable wait state options: 2 to 31 CCLK Digital audio interface includes six serial ports, two pre- cision clock generators, an input data port, three programmable timers and a signal routing unit Serial ports provide: Six dual data line serial ports that operate at up to 50 Mbits/s for a 200 MHz core on each data line each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair Left-justified sample pair and I2S support, programmable direction for up to 24 simultaneous receive or transmit channels using two I2S compatible stereo devices per serial port TDM support for telecommunications interfaces including 128 TDM channel support for telephony interfaces such as H.100/H.110 Up to 12 TDM stream support, each with 128 channels per frame Companding selection on a per channel basis in TDM mode Input data port provides an additional input path to the DSP core configurable as either eight channels of I2S or serial data or as seven channels plus a single 20-bit wide syn- chronous parallel data acquisition port Supports receive audio channel data in I2S, left-justified sample pair, or right-justified mode Signal routing unit provides configurable and flexible connections between all DAI components, six serial ports, an input data port, two precision clock generators, three timers, 10 interrupts, six flag inputs, six flag outputs, and 20 SRU I/O pins Serial peripheral interface Master or slave serial boot through SPI Full-duplex operation Master-slave mode multimaster support Open drain outputs Programmable baud rates, clock polarities, and phases 3 Muxed Flag/IRQ lines 1 Muxed Flag/Timer expired line ROM based security features: JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multi- plier/divider ratios JTAG background telemetry for enhanced emulation features IEEE 1149.1 JTAG standard test access port and on-chip emulation Dual voltage: 3.3 V I/O, 1.2 V core Available in 136-ball BGA and 144-lead LQFP packages Lead free packages are also available

MAX1999EEI引脚说明： 8 - 32位和16 - 32位字包装选择可编程等待状态的选择：2至31个CCLK数字音频接口包括6个串行端口，两个前643时钟发生器，输入数据端口， 3可编程定时器和一个信号路由单元串行端口提供：六双串口数据线，在高达50 Mbps的操作/为200兆赫的每个数据行每个人都有一个时钟，帧同步的核心秒，和两个数据可以作为任何一个接收器或发射器对左对齐和I2S配对样本的支持下，最多可同时接收或传送24个频道，每使用两个系列的I2S兼容立体声设备配置可编程方向线；港口的TDM通信接口，包括支持128个电话接口的TDM的渠道，如H.100/H.110支持多达12个的TDM流的支持下，每帧128个频道每个压缩扩展每通道的基础上选择在TDM模式输入数据端口提供了一个额外的输入路径的DSP核心配置为I2S或串行数据或7加一个20位宽的SYN -异步的并行数据采集接口通道或8通道；支持接收通道I2S音频数据，左对齐样本对，或右对齐模式信号路由单元组件之间提供所有戴配置和灵活的连接，6个串行端口，一个输入数据端口，两个精密时钟发生器，3个定时器，10个中断，六旗投入，产出6个旗，20曼谷南南区域股的I / O管脚串行外设接口的硕士或奴隶通过SPI串行启动全双工运作主从模式多主机支持开漏输出可编程波特率，时钟极性和第三期合并调制旗/ IRQ线路1合并调制旗/定时器过期线光盘的防伪特征：JTAG的访问与64位受保护的关键允许内存内存可分配给程序访问控制的限制下对敏感地区有一个代码锁相环/遥测分比率为背景的JTAG仿真功能增强的IEEE 1149.1 JTAG标准测试访问端口的软件和硬件多钳各种各样和片上仿真双电压：3.3六/输出，可在1.2 V核心136球BGA封装和144引脚LQFP封装无铅封装，也可

TDA4864 Pinout: 8- to 32-bit and 16- to 32-bit word packing options Programmable wait state options: 2 to 31 CCLK Digital audio interface includes six serial ports, two pre- cision clock generators, an input data port, three programmable timers and a signal routing unit Serial ports provide: Six dual data line serial ports that operate at up to 50 Mbits/s for a 200 MHz core on each data line each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair Left-justified sample pair and I2S support, programmable direction for up to 24 simultaneous receive or transmit channels using two I2S compatible stereo devices per serial port TDM support for telecommunications interfaces including 128 TDM channel support for telephony interfaces such as H.100/H.110 Up to 12 TDM stream support, each with 128 channels per frame Companding selection on a per channel basis in TDM mode Input data port provides an additional input path to the DSP core configurable as either eight channels of I2S or serial data or as seven channels plus a single 20-bit wide syn- chronous parallel data acquisition port Supports receive audio channel data in I2S, left-justified sample pair, or right-justified mode Signal routing unit provides configurable and flexible connections between all DAI components, six serial ports, an input data port, two precision clock generators, three timers, 10 interrupts, six flag inputs, six flag outputs, and 20 SRU I/O pins Serial peripheral interface Master or slave serial boot through SPI Full-duplex operation Master-slave mode multimaster support Open drain outputs Programmable baud rates, clock polarities, and phases 3 Muxed Flag/IRQ lines 1 Muxed Flag/Timer expired line ROM based security features: JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multi- plier/divider ratios JTAG background telemetry for enhanced emulation features IEEE 1149.1 JTAG standard test access port and on-chip emulation Dual voltage: 3.3 V I/O, 1.2 V core Available in 136-ball BGA and 144-lead LQFP packages Lead free packages are also available

TDA4864引脚说明： 8 - 32位和16 - 32位字包装选择可编程等待状态的选择：2至31个CCLK数字音频接口包括6个串行端口，两个前643时钟发生器，输入数据端口， 3可编程定时器和一个信号路由单元串行端口提供：六双串口数据线，在高达50 Mbps的操作/为200兆赫的每个数据行每个人都有一个时钟，帧同步的核心秒，和两个数据可以作为任何一个接收器或发射器对左对齐和I2S样本对支持，最多可同时接收或传送24个频道，每使用两个系列的I2S兼容立体声设备配置可编程方向线；港口的TDM通信接口，包括支持128个电话接口的TDM的渠道，如H.100/H.110支持多达12个的TDM流的支持下，每帧128个频道每个压缩扩展每通道的基础上选择在TDM模式输入数据端口提供了一个额外的输入路径的DSP核心配置为I2S或串行数据或7加一个20位宽的SYN -异步的并行数据采集接口通道或8通道；支持接收通道I2S音频数据，左对齐样本对，或右对齐模式信号路由单元组件之间提供所有戴配置和灵活的连接，6个串行端口，一个输入数据端口，两个精密时钟发生器，3个定时器，10个中断，六旗投入，产出6个旗，20曼谷南南区域股的I / O管脚串行外设接口的硕士或奴隶通过SPI串行启动全双工运作主从模式多主机支持开漏输出可编程波特率，时钟极性和第三期合并调制旗/ IRQ线路1合并调制旗/定时器过期线光盘的防伪特征：JTAG的访问与64位受保护的关键允许内存内存可分配给程序访问控制的限制下对敏感地区有一个代码锁相环/分比率背景遥测的JTAG仿真功能增强的IEEE 1149.1 JTAG标准测试访问端口软件和硬件多钳各种各样和片上仿真双电压：3.3六/输出，可在1.2 V核心136球BGA封装和144引脚LQFP封装无铅封装，也可

Main products: 1: Japan OMRON (between relays, time relays, temperature controller, photoelectric switch, proximity switches, trip switches, programmable logic controller) 2: Korea LG motor (air switch, contactors, thermal relays, magnetic starter, programmable logic controller) 3: Japan's Fuji motor (air switch, contactor, thermal relay, temperature controller, time relay, inverter, programmable controller, button, indicator light) 4: Japan's Mitsubishi Electric (air switch, contactors, thermal relays, Inverter, programmable controllers, servo series) 5: Korea AUTONICS (Photoelectric switch, close to-day clearance, temperature controller) 6: Taiwan CKC (time relay, the water level controller, solid state relays, counters) I Division otherwise operating Siemens, Schneider, and Stephen, RKC, days too, Hanyoung brands, such as industrial automation components, category range.

1：日本OMRON（中间继电器，时间继电器，温控器，光电开关，接近开关，行程开关，可编程控制器）2：韩国LG电机(空气开关，接触器，热继电器，磁力起动器，可编程控制器)3：日本富士电机（空气开关，接触器，热继电器，温控器，时间继电器，变频器，可编程控制器，按钮，指示灯）4：日本三菱电机（空气开关，接触器，热继电器，变频器，可编程控制器，伺服系列）5：韩国AUTONICS（光电开关，接近天关，温控器）6：台湾CKC（时间继电器，水位控制器，固态继电器，计数器）我司另有经营西门子、施耐德、和泉、RKC、天得、韩荣等品牌的自动化工控元件，品类繁多。

Pinout: C High-performance 32-bit RISC Architecture C High-density 16-bit Instruction Set C Leader in MIPS/Watt C Little-endian C Embedded ICE (In-circuit Emulation) 8-, 16- and 32-bit Read and Write Support 256K Bytes of On-chip SRAM C 32-bit Data Bus C Single-clock Cycle Access Fully Programmable External Bus Interface C Maximum External Address Space of 64M Bytes C Up to Eight Chip Selects C Software Programmable 8/16-bit External Data Bus Eight-level Priority, Individually Maskable, Vectored Interrupt Controller C Four External Interrupts, including a High-priority, Low-latency Interrupt Request 32 Programmable I/O Lines Three-channel 16-bit Timer/Counter C Three External Clock Inputs C Two Multi-purpose I/O Pins per Channel Two USARTs C Two Dedicated Peripheral Data Controller Channels per USART Programmable Watchdog Timer Advanced Power-saving Features C CPU and Peripheral Can be Deactivated Individually Fully Static Operation: C 0 Hz to 75 MHz Internal Frequency Range at VDDCORE = 1.8V, 85C 2.7V to 3.6V I/O Operating Range 1.65V to 1.95V Core Operating Range -40C to +85C Temperature Range Available in 100-lead TQFP Package

M5L8253P-5引脚说明： C型高性能32位RISC架构C高密度以MIPS /瓦C小端C十六位指令集C领袖嵌入式冰8 - 16 -位和32位的读写支持256K的片上SRAM的 32位数据总线C单时钟周期存取字节完全可编程的外部总线接口C最大的外部地址空间的64M字节多达8个C芯片选择C软件可编程8位外部数据总线8级优先级，独立可屏蔽，向量中断控制器C四外部中断，其中包括一个高优先级，低延迟中断要求32个可编程I / O口线三通道16位定时器/计数器C三个外部时钟输入C两多用途I / O引脚每通道2个通用同步C两专用外设数据控制器通道每个USART可编程看门狗定时器先进的节能特性 CPU和外设可停用独立全静态工作中：C 0 Hz至75 MHz的频率范围内的VDDCORE = 1.8，85℃2.7V到3.6VI / O的操作1.65V到1.95V范围核心工作电压范围在- 40C至+85 C温度范围内使用的100引脚TQFP封装

Key management is the core problem of network system security, which deals with the correlative problems from key being generated to ultimately destroyed; it includes system initialization, key generation, key encasement, key distribution, key storage, key renovation, key destruction, etc. Thereinto key distribution and key storage are the two most intractable taches of key management.

密钥管理问题是网络系统安全中首要的核心问题，它是处理密钥自产生到最终销毁的整个过程中的有关问题，包括系统的初始化，密钥的产生、装入、分配、存储、更新、吊销和销毁等内容，而密钥的分配和存储是密钥管理中最为棘手的两个环节。

The IRS2158D features include programmable preheat and run frequencies, programmable preheat time, closed-loop half-bridge ignition current regulation, programmable end-of-life protection, brownout protection and low input offset op amp.

IRS2158D的主要特性包括可编程的灯预热和运行频率，可编程的预热时间，闭环半桥点燃电流调整，可编程灯寿命终期保护，输入低电压保护和低输入失调的运算放大器。

This paper proposes the research situation of the programmable cryptographic technique and the charac teristics of the programmable cryptograph,including the aspects to be concerned about in the development of the programmable cryptograph.

文中给出了可编程密码技术的研究现状，可编程密码的特点，及在开展可编程密码研究时应注意的问题。

MC44144 Pinout: Flyback and Synchronous Rectifier Apps Provides Complementary Auxiliary Driver with Programmable Deadtime (Turn-On Delay) between AUX and MAIN Switches Peak Current-Mode Control with 0.5-V Cycle-by-Cycle Current Limiting Hiccup Mode 0.75-V Current Limit TrueDrivet 2-A Sink, 2-A Source Outputs 110-V Input Startup Device Trimmed Internal Bandgap Reference for Accurate Line UV and Line OV Threshold Programmable Slope Compensation High-Performance 1.0-MHz Synchronizable Oscillator with Internal Timing Capacitor Precise Programmable Maximum Duty Cycle PB-Free Lead Finish Package

MC44144引脚说明：反激式同步整流和应用服务提供补充辅助与可编程死区时间之间的辅助和主开关峰值电流模式控制0.5 - V的逐周期电流限制打嗝模式0.75 - V的电流限制TrueDrivet 2 - A号水槽，2 -阿源精确的线路过压阈值线UV和可编程斜率补偿高性能1.0 - MHz的振荡器可同步输出110 V输入启动装置边内部带隙基准，内置精密程控定时电容最大占空比无铅引脚完成包

Eatures · Compatible with MCS-51 Products · 2K Bytes of Reprogrammable Flash Memory – Endurance: 1,000 Write/Erase Cycles · 2.7V to 6V Operating Range · Fully Static Operation: 0 Hz to 24 MHz · Two-Level Program Memory Lock · 128 x 8-Bit Internal RAM · 15 Programmable I/O Lines · Two 16-Bit Timer/Counters · Six Interrupt Sources · Programmable Serial UART Channel · Direct LED Drive Outputs · On-Chip Analog Comparator · Low Power Idle and Power Down Modes Description The AT89C2051 is a low-voltage, high-performance CMOS 8-bit microcomputer with 2K Bytes of Flash programmable and erasable read only memory.

eatures ·兼容MCS - 51的产品·及2k字节的编程快闪记忆体-耐力： 1 000写/擦除周期·在2.7 V至6 V的操作范围·完全静态的运作： 0 Hz至24兆赫·两个层次的程式记忆体锁· 128 × 8位内部RAM · 15个可编程I / O线·两个16位定时器/计数器· 6中断源·可编程串行UART的频道·直接驱动LED产出·单晶片模拟比较·低功耗的闲置和掉电模式描述该AT89C2051的是一个低电压，高性能的CMOS 8位微机与及2k字节的Flash可编程和可擦除唯读记忆体。

The method includes steps: digital watermark technique is adopted to hide information of key data in not key data codes of compressed image; under protection of digital watermark, using protective backup for key data detects whether normal transmitted key data is correct or not so as to detect error code; carrying out cyclic mutual backup by using macro blocks in same positions in front and back macro block set; embedding coded motion vector in form of digital watermark to DCT transformation coefficient, and ensuring that video data are not influenced as best as one can; when error code occurs, if key data backup is correct, then the backup replaces former key data; otherwise, using mean value of key data in adjacent macro blocks within same frame to replace former key data approximately.

本发明中，采用数字水印技术在压缩图像的非关键数据编码中隐藏关键数据信息；通过数字水印保护下的关键数据保护备份来检测正常传输的关键数据是否正确，由此来检测传输误码；用前后宏块组中相同位置的宏块进行循环相互备份；对运动向量进行编码，然后以数字水印的形式嵌入到相对不重要的DCT变换系数中，同时保证视频数据尽量不受影响；在误码发生时，如果关键数据备份正确，则直接替代原关键数据，否则用同一帧内相邻宏块的关键数据的平均值近似替代原关键数据。

Fostering the concept of multi-culture firmly and mastering the development of advanced culture correctly are conductive to resisting terrorism, separatism of nationalities and ultraism of religion, which is of great academic theoretical, immediate and profound historical si...

牢固树立多元文化的理念和正确把握先进文化的发展方向，有助于在世界范围内自觉地抵制恐怖主义，民族分裂主义和宗教极端主义。不仅具有重大的学术理论意义，而且也具有重大的现实意义和深远的历史意义。

But if anyone walks in the night, he stumbles, because the light is not in him.

11：10 若在黑夜行走，就必碰跌，因为那光不在他里面。