查询词典 process input output

Each device features receiver high input impedance and input hysteresis for increased noise immunity, and input sensitivity of 200 mV over a common-mode input voltage range from C 0.3 V to 5.5 V. When the inputs are open circuited, the outputs are in the high logic state.

每个器件具有增加抗噪声接收器高输入阻抗和输入滞后，以及投入200毫伏以上的共模输入电压范围从C 0.3 V至5.5五，当输入开路时，输出的是高灵敏度逻辑状态。

MAX1999EEI Pinout: 8- to 32-bit and 16- to 32-bit word packing options Programmable wait state options: 2 to 31 CCLK Digital audio interface includes six serial ports, two pre- cision clock generators, an input data port, three programmable timers and a signal routing unit Serial ports provide: Six dual data line serial ports that operate at up to 50 Mbits/s for a 200 MHz core on each data line each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair Left-justified sample pair and I2S support, programmable direction for up to 24 simultaneous receive or transmit channels using two I2S compatible stereo devices per serial port TDM support for telecommunications interfaces including 128 TDM channel support for telephony interfaces such as H.100/H.110 Up to 12 TDM stream support, each with 128 channels per frame Companding selection on a per channel basis in TDM mode Input data port provides an additional input path to the DSP core configurable as either eight channels of I2S or serial data or as seven channels plus a single 20-bit wide syn- chronous parallel data acquisition port Supports receive audio channel data in I2S, left-justified sample pair, or right-justified mode Signal routing unit provides configurable and flexible connections between all DAI components, six serial ports, an input data port, two precision clock generators, three timers, 10 interrupts, six flag inputs, six flag outputs, and 20 SRU I/O pins Serial peripheral interface Master or slave serial boot through SPI Full-duplex operation Master-slave mode multimaster support Open drain outputs Programmable baud rates, clock polarities, and phases 3 Muxed Flag/IRQ lines 1 Muxed Flag/Timer expired line ROM based security features: JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multi- plier/divider ratios JTAG background telemetry for enhanced emulation features IEEE 1149.1 JTAG standard test access port and on-chip emulation Dual voltage: 3.3 V I/O, 1.2 V core Available in 136-ball BGA and 144-lead LQFP packages Lead free packages are also available

MAX1999EEI引脚说明： 8 - 32位和16 - 32位字包装选择可编程等待状态的选择：2至31个CCLK数字音频接口包括6个串行端口，两个前643时钟发生器，输入数据端口， 3可编程定时器和一个信号路由单元串行端口提供：六双串口数据线，在高达50 Mbps的操作/为200兆赫的每个数据行每个人都有一个时钟，帧同步的核心秒，和两个数据可以作为任何一个接收器或发射器对左对齐和I2S配对样本的支持下，最多可同时接收或传送24个频道，每使用两个系列的I2S兼容立体声设备配置可编程方向线；港口的TDM通信接口，包括支持128个电话接口的TDM的渠道，如H.100/H.110支持多达12个的TDM流的支持下，每帧128个频道每个压缩扩展每通道的基础上选择在TDM模式输入数据端口提供了一个额外的输入路径的DSP核心配置为I2S或串行数据或7加一个20位宽的SYN -异步的并行数据采集接口通道或8通道；支持接收通道I2S音频数据，左对齐样本对，或右对齐模式信号路由单元组件之间提供所有戴配置和灵活的连接，6个串行端口，一个输入数据端口，两个精密时钟发生器，3个定时器，10个中断，六旗投入，产出6个旗，20曼谷南南区域股的I / O管脚串行外设接口的硕士或奴隶通过SPI串行启动全双工运作主从模式多主机支持开漏输出可编程波特率，时钟极性和第三期合并调制旗/ IRQ线路1合并调制旗/定时器过期线光盘的防伪特征：JTAG的访问与64位受保护的关键允许内存内存可分配给程序访问控制的限制下对敏感地区有一个代码锁相环/遥测分比率为背景的JTAG仿真功能增强的IEEE 1149.1 JTAG标准测试访问端口的软件和硬件多钳各种各样和片上仿真双电压：3.3六/输出，可在1.2 V核心136球BGA封装和144引脚LQFP封装无铅封装，也可

TDA4864 Pinout: 8- to 32-bit and 16- to 32-bit word packing options Programmable wait state options: 2 to 31 CCLK Digital audio interface includes six serial ports, two pre- cision clock generators, an input data port, three programmable timers and a signal routing unit Serial ports provide: Six dual data line serial ports that operate at up to 50 Mbits/s for a 200 MHz core on each data line each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair Left-justified sample pair and I2S support, programmable direction for up to 24 simultaneous receive or transmit channels using two I2S compatible stereo devices per serial port TDM support for telecommunications interfaces including 128 TDM channel support for telephony interfaces such as H.100/H.110 Up to 12 TDM stream support, each with 128 channels per frame Companding selection on a per channel basis in TDM mode Input data port provides an additional input path to the DSP core configurable as either eight channels of I2S or serial data or as seven channels plus a single 20-bit wide syn- chronous parallel data acquisition port Supports receive audio channel data in I2S, left-justified sample pair, or right-justified mode Signal routing unit provides configurable and flexible connections between all DAI components, six serial ports, an input data port, two precision clock generators, three timers, 10 interrupts, six flag inputs, six flag outputs, and 20 SRU I/O pins Serial peripheral interface Master or slave serial boot through SPI Full-duplex operation Master-slave mode multimaster support Open drain outputs Programmable baud rates, clock polarities, and phases 3 Muxed Flag/IRQ lines 1 Muxed Flag/Timer expired line ROM based security features: JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multi- plier/divider ratios JTAG background telemetry for enhanced emulation features IEEE 1149.1 JTAG standard test access port and on-chip emulation Dual voltage: 3.3 V I/O, 1.2 V core Available in 136-ball BGA and 144-lead LQFP packages Lead free packages are also available

TDA4864引脚说明： 8 - 32位和16 - 32位字包装选择可编程等待状态的选择：2至31个CCLK数字音频接口包括6个串行端口，两个前643时钟发生器，输入数据端口， 3可编程定时器和一个信号路由单元串行端口提供：六双串口数据线，在高达50 Mbps的操作/为200兆赫的每个数据行每个人都有一个时钟，帧同步的核心秒，和两个数据可以作为任何一个接收器或发射器对左对齐和I2S样本对支持，最多可同时接收或传送24个频道，每使用两个系列的I2S兼容立体声设备配置可编程方向线；港口的TDM通信接口，包括支持128个电话接口的TDM的渠道，如H.100/H.110支持多达12个的TDM流的支持下，每帧128个频道每个压缩扩展每通道的基础上选择在TDM模式输入数据端口提供了一个额外的输入路径的DSP核心配置为I2S或串行数据或7加一个20位宽的SYN -异步的并行数据采集接口通道或8通道；支持接收通道I2S音频数据，左对齐样本对，或右对齐模式信号路由单元组件之间提供所有戴配置和灵活的连接，6个串行端口，一个输入数据端口，两个精密时钟发生器，3个定时器，10个中断，六旗投入，产出6个旗，20曼谷南南区域股的I / O管脚串行外设接口的硕士或奴隶通过SPI串行启动全双工运作主从模式多主机支持开漏输出可编程波特率，时钟极性和第三期合并调制旗/ IRQ线路1合并调制旗/定时器过期线光盘的防伪特征：JTAG的访问与64位受保护的关键允许内存内存可分配给程序访问控制的限制下对敏感地区有一个代码锁相环/分比率背景遥测的JTAG仿真功能增强的IEEE 1149.1 JTAG标准测试访问端口软件和硬件多钳各种各样和片上仿真双电压：3.3六/输出，可在1.2 V核心136球BGA封装和144引脚LQFP封装无铅封装，也可

Accurate analog power is to provide power, digital chip, amplifiers, microcontroller is the voltage required by A/D sampling data output voltage, and comparison, if there is A deviation is the limit, adjust output signal output and closure, alarm, The working process of the working status, manostat by SCM outputs drive LED display, Display circuit used to display the size of the output voltage of power.

准确说就是模拟电源提供各个芯片电源、数码管、放大器所需电压，单片机则通过A/D采样输出电压，与设定值进行比较，若有偏差则调整输出，越限则输出报警信号并截流；工作过程中，稳压电源的工作状态均由单片机输出驱动LED显示；显示电路用于显示电源输出电压的大小。

Connection Panel: One DVI port, one VGA input, one VGA monitor pass-through, one composite video, one s-video, one USB port for mouse control, one RJ-45 wired networking port, one 1/8" audio input, one L/R RCA audio input, one 1/8" audio output, one RS-232 port, Kensington lock point.

连接面板：一个DVI端口，一个VGA输入，一个VGA监视器传递，一个复合视频，一个S端子，一个USB端口的鼠标控制，一个使用RJ - 45有线网络端口，一个1 / 8 "音频输入，一个左/右的RCA音频输入，一个1 / 8 "的音频输出，一个RS - 232端口，肯辛顿锁点。

This method employs the exponential pulse time series as input to excite CFD model, which can provide slick aerodynamic forces acting on the body through CFD simulation, Then discrete time aerodynamic models, defined among interesting range of frequency, can be trained based on the CFD input output relationship, those models can he implemented thereafter to simulate aerodynamic response for simple-harmonic input of displacement with suitable frequency.

该方法采用具有连续频谱分布且位移光滑的指数脉冲序列为CFD模型运动的输入，通过数值模拟得到作用在模型上的气动力。利用已知的输入和气动力建立起反映系统气动力特征的离散时间气动模型。

As a DC/DC basic structure is adopted, the operational amplifier leads the non inverting input end voltage of the error amplifier to follow the input voltage linearly, thus realizing the linear following relation between the output voltage and the input voltage.

由于采用DC/DC的基础结构，增加运算放大器使误差放大器的同相输入端电压与输入电压线性跟随，从而实现输出电压与输入电压的线性跟随关系。

The result indicates that the output power oscillates and weakens along with increasing input power,and its oscillation period depends on the distance between the medium and beam focal point.Limiter′s limiting ability will decrease if waist size of the incident Gaussian beam and the aperture size increase.With a fixed input power scope,medium′s best limiting position will move towards the focal point if waist size of Gaussian beam and the aperture size increase,but the best limiting position will change a lot with different input power scopes.

结果表明：限幅器的出射功率随入射功率的增加衰减振荡，其振荡周期取决于介质相对于光束焦点的位置；限幅器的限幅能力随入射光束腰半径和光阑孔径的变大而减弱；入射功率范围固定，入射光束腰半径和光阑孔径增大时，介质的最佳限幅位置向入射光束的焦点靠近，但是在某些入射功率范围内会存在多个最佳限幅位置；光限幅器的箝位输出功率随光阑线性透过率的增加存在线性增加和非线性增加两个不同区域，实际应用中应在线性增加区域确定光阑孔径的大小。

Based on them, this paper proposes evaluation indexof fund performance from the aspect of finance, investor and interiormanagement. Considering the limitation of data envelopment analysis approach usedto evaluate fund performance, such as conventional DEA models can not considerinputs and outputs of evaluation units simultaneously, and an input-oriented DEAmodel and output-oriented DEA model often produce different evaluation results,this paper proposes a general form of DEA model which is input- andoutput-oriented by using multi-objective optimization and fuzzy set theory. Sincethe general form of DEA model can be transformed into a conventional input oroutput oriented DEA model by using special membership functions, it can beseemed as a nature extense of conventional DEA models, and a conventionalmodel can be regarded as a special case of DEA mdoel with general form.

针对现有基金绩效评价方法中较具优越性的数据包络分析方法的不足，如传统DEA模型不能同时综合考虑评价单元的输入和输出，以及分别采用面向输入和面向输出DEA模型评价基金绩效时，常常出现不一致的评价结果等，本文以多目标优化与模糊集合理论为工具，提出了一种能够同时面向输入和输出的DEA一般形式模型，并通过选择一些特殊的模糊集合隶属函数，使得这种DEA一般形式模型成为传统DEA模型的自然推广，而传统DEA模型是该模型的特殊形式。

Therefore, the exact relation between the unbalanced input voltage and the noncharacteristic harmonics of the output voltage in the 12-pulse rectifier system is obtained. In addition, the relation between the input current and the imbalance of the input voltage is obtained, which could help to choose the filter elements and exactly analyze the characteristics of the no controlled rectifier circuit.

利用精确的开关函数，推导了多脉波整流系统输入不平衡电压与输出电压非特征谐波的精确关系，进而得到电阻、电感负载时系统输入电流与输入电压不平衡度的关系，为精确地选择滤波元件做了有意义的探索。

For the head-teacher of the class said that I had seriously broken the school rules,which led me to a three-day suspend class.

为什么呢？因为我的班主任说我严重的违反了校规，于是让我停课三天。

Many of them believe that the conversion of thousands of working-class folk in England spared that nation from the mass carnage and the tyranny that came with the revolution in France.

他们之中有许多人相信，在英国数以千计的劳工阶级之悔改信主使英国免於遭受如法国大革命所造成的大屠杀和专制暴政。