查询词典 parallel line

Taking the laser diode line generator as the light source, the parallel laser screen unit was formed by using aplanatic cylindrical Fresnel lens with long focal length. By splicing seamlessly with multiple parallel laser-screen units, the large area laser screen can he constructed.

以半导体激光线发生器为光源，用长焦距消球差的柱面菲涅耳透镜形成平行激光幕单元，通过多个平行激光幕单元的无缝拼接可形成大面积靶面。

WHEN A STRAIGHE LINE TURNS IN SPACE PARALLEL TO AN AXIS , IT GENERATES A CYLINDER . WHEN IT IS NOT PARALLEL , IT GENERATES A HYPERBOLID OF REVOLUTION OF ONE SHEET . A HALF-HYPERBOLOID IS THE THE IDEAL SHAPE FOR A BELL

这种柔和的平面在传说建筑中没有应用过，但是由于它具有良好的采光、传音和散重能力，所以高迪在柱子、柱头、屋顶，天窗和大钟中曾多次使用。

To the side of the center line move over 2 and draw a line parallel to the center line.

到中线一侧移动了2，划一条平行于中线。

This paper proposes a network parallel computing approach for hydromechanical problem on rectangle domain using line-relaxation method.A multigrid method with virtual nodes for the second kind boundary condition and a parallel scheme of zebra-line-relaxation multigrid technique are discussed.

提出了一个用线松弛法解决长矩形区域流场问题的网络并行方案，详细讨论了使用虚拟节点处理第2类边值条件的多重网格技术和斑马线松弛多重网格技术的并行化方法，给出了从计算方法到它的并行化的完整过程。

Finally, calculate in series power flow of a line after overload line tripping to confirm the parallel transmission section of overload line.

线路过载后，依序比较回路中线路与过载线路的潮流方向，以判定其是否属于过载线路的并行输电断面。

One line from inferior edge of anteroinferior iliac spine to the crossing point of posterior gluteal line and posterior iliac crest was defined as A line, which was parallel to the Chiotic line (the crossing point of Chiotic line and posterior iliac crest called CLIC point).

设定髂前下棘下缘向后经过臀后线与骼嵴后部交叉点的连线截面为A线截面，此线与Chiotic线平行（Chiotic线与髂嵴后部交叉点称为CLIC点）。

By researching and analyzing Defending the Goal Line, the paper puts forward alterable goal line, and also researches two methods: the alterable parallel goal line and the alterable across goal line, that can display the defensive effect of the goalie sufficiently.

在研究和分析基于防线的守门员跑位模式的基础上，论文打破了单条防线对守门员的限制，提出了可变防线的思想，研究了基于平行可变防线和交叉可变防线两种守门员防守模型，更好地发挥了守门员的防守作用。

We focus on resolving the following problems in FTP, that is how to guarantee the measurement accuracy of FTP when the connect line between the exit pupil of the projecting lens and that of the entrance pupil of the imaging lens is not parallel to the reference, or the two pupils are not coplanar, or neither the connect line parallel to the reference nor the two pupils coplanar.

推导出了适用范围更广泛的变形条纹描述公式和相位计算方法以及相位—高度映射算法。对于传统的傅里叶变换轮廓术测量系统而言，由于要求投影仪出瞳与摄像机入瞳连线与参考面平行，而且要求投影仪光轴与摄像机光轴共面，所以它可以被看作是本文所提出系统结构在该种情况下的一种特例。

MAX1999EEI Pinout: 8- to 32-bit and 16- to 32-bit word packing options Programmable wait state options: 2 to 31 CCLK Digital audio interface includes six serial ports, two pre- cision clock generators, an input data port, three programmable timers and a signal routing unit Serial ports provide: Six dual data line serial ports that operate at up to 50 Mbits/s for a 200 MHz core on each data line each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair Left-justified sample pair and I2S support, programmable direction for up to 24 simultaneous receive or transmit channels using two I2S compatible stereo devices per serial port TDM support for telecommunications interfaces including 128 TDM channel support for telephony interfaces such as H.100/H.110 Up to 12 TDM stream support, each with 128 channels per frame Companding selection on a per channel basis in TDM mode Input data port provides an additional input path to the DSP core configurable as either eight channels of I2S or serial data or as seven channels plus a single 20-bit wide syn- chronous parallel data acquisition port Supports receive audio channel data in I2S, left-justified sample pair, or right-justified mode Signal routing unit provides configurable and flexible connections between all DAI components, six serial ports, an input data port, two precision clock generators, three timers, 10 interrupts, six flag inputs, six flag outputs, and 20 SRU I/O pins Serial peripheral interface Master or slave serial boot through SPI Full-duplex operation Master-slave mode multimaster support Open drain outputs Programmable baud rates, clock polarities, and phases 3 Muxed Flag/IRQ lines 1 Muxed Flag/Timer expired line ROM based security features: JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multi- plier/divider ratios JTAG background telemetry for enhanced emulation features IEEE 1149.1 JTAG standard test access port and on-chip emulation Dual voltage: 3.3 V I/O, 1.2 V core Available in 136-ball BGA and 144-lead LQFP packages Lead free packages are also available

MAX1999EEI引脚说明： 8 - 32位和16 - 32位字包装选择可编程等待状态的选择：2至31个CCLK数字音频接口包括6个串行端口，两个前643时钟发生器，输入数据端口， 3可编程定时器和一个信号路由单元串行端口提供：六双串口数据线，在高达50 Mbps的操作/为200兆赫的每个数据行每个人都有一个时钟，帧同步的核心秒，和两个数据可以作为任何一个接收器或发射器对左对齐和I2S配对样本的支持下，最多可同时接收或传送24个频道，每使用两个系列的I2S兼容立体声设备配置可编程方向线；港口的TDM通信接口，包括支持128个电话接口的TDM的渠道，如H.100/H.110支持多达12个的TDM流的支持下，每帧128个频道每个压缩扩展每通道的基础上选择在TDM模式输入数据端口提供了一个额外的输入路径的DSP核心配置为I2S或串行数据或7加一个20位宽的SYN -异步的并行数据采集接口通道或8通道；支持接收通道I2S音频数据，左对齐样本对，或右对齐模式信号路由单元组件之间提供所有戴配置和灵活的连接，6个串行端口，一个输入数据端口，两个精密时钟发生器，3个定时器，10个中断，六旗投入，产出6个旗，20曼谷南南区域股的I / O管脚串行外设接口的硕士或奴隶通过SPI串行启动全双工运作主从模式多主机支持开漏输出可编程波特率，时钟极性和第三期合并调制旗/ IRQ线路1合并调制旗/定时器过期线光盘的防伪特征：JTAG的访问与64位受保护的关键允许内存内存可分配给程序访问控制的限制下对敏感地区有一个代码锁相环/遥测分比率为背景的JTAG仿真功能增强的IEEE 1149.1 JTAG标准测试访问端口的软件和硬件多钳各种各样和片上仿真双电压：3.3六/输出，可在1.2 V核心136球BGA封装和144引脚LQFP封装无铅封装，也可

TDA4864 Pinout: 8- to 32-bit and 16- to 32-bit word packing options Programmable wait state options: 2 to 31 CCLK Digital audio interface includes six serial ports, two pre- cision clock generators, an input data port, three programmable timers and a signal routing unit Serial ports provide: Six dual data line serial ports that operate at up to 50 Mbits/s for a 200 MHz core on each data line each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair Left-justified sample pair and I2S support, programmable direction for up to 24 simultaneous receive or transmit channels using two I2S compatible stereo devices per serial port TDM support for telecommunications interfaces including 128 TDM channel support for telephony interfaces such as H.100/H.110 Up to 12 TDM stream support, each with 128 channels per frame Companding selection on a per channel basis in TDM mode Input data port provides an additional input path to the DSP core configurable as either eight channels of I2S or serial data or as seven channels plus a single 20-bit wide syn- chronous parallel data acquisition port Supports receive audio channel data in I2S, left-justified sample pair, or right-justified mode Signal routing unit provides configurable and flexible connections between all DAI components, six serial ports, an input data port, two precision clock generators, three timers, 10 interrupts, six flag inputs, six flag outputs, and 20 SRU I/O pins Serial peripheral interface Master or slave serial boot through SPI Full-duplex operation Master-slave mode multimaster support Open drain outputs Programmable baud rates, clock polarities, and phases 3 Muxed Flag/IRQ lines 1 Muxed Flag/Timer expired line ROM based security features: JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multi- plier/divider ratios JTAG background telemetry for enhanced emulation features IEEE 1149.1 JTAG standard test access port and on-chip emulation Dual voltage: 3.3 V I/O, 1.2 V core Available in 136-ball BGA and 144-lead LQFP packages Lead free packages are also available

TDA4864引脚说明： 8 - 32位和16 - 32位字包装选择可编程等待状态的选择：2至31个CCLK数字音频接口包括6个串行端口，两个前643时钟发生器，输入数据端口， 3可编程定时器和一个信号路由单元串行端口提供：六双串口数据线，在高达50 Mbps的操作/为200兆赫的每个数据行每个人都有一个时钟，帧同步的核心秒，和两个数据可以作为任何一个接收器或发射器对左对齐和I2S样本对支持，最多可同时接收或传送24个频道，每使用两个系列的I2S兼容立体声设备配置可编程方向线；港口的TDM通信接口，包括支持128个电话接口的TDM的渠道，如H.100/H.110支持多达12个的TDM流的支持下，每帧128个频道每个压缩扩展每通道的基础上选择在TDM模式输入数据端口提供了一个额外的输入路径的DSP核心配置为I2S或串行数据或7加一个20位宽的SYN -异步的并行数据采集接口通道或8通道；支持接收通道I2S音频数据，左对齐样本对，或右对齐模式信号路由单元组件之间提供所有戴配置和灵活的连接，6个串行端口，一个输入数据端口，两个精密时钟发生器，3个定时器，10个中断，六旗投入，产出6个旗，20曼谷南南区域股的I / O管脚串行外设接口的硕士或奴隶通过SPI串行启动全双工运作主从模式多主机支持开漏输出可编程波特率，时钟极性和第三期合并调制旗/ IRQ线路1合并调制旗/定时器过期线光盘的防伪特征：JTAG的访问与64位受保护的关键允许内存内存可分配给程序访问控制的限制下对敏感地区有一个代码锁相环/分比率背景遥测的JTAG仿真功能增强的IEEE 1149.1 JTAG标准测试访问端口软件和硬件多钳各种各样和片上仿真双电压：3.3六/输出，可在1.2 V核心136球BGA封装和144引脚LQFP封装无铅封装，也可

Chrysanthemum of 10 thousand birthday is lax to edaphic requirement, with the arenaceous qualitative loam with fecund, good drainage had better.

万寿菊对土壤要求不严，以肥沃。排水良好的砂质壤土为好。

He unstepped the mast and furled the sail and tied it.

他拔下桅杆，把帆卷起，系住。