查询词典 parallel line

To the side of the center line move over 2 and draw a line parallel to the center line.

到中线一侧移动了2，划一条平行于中线。

Finally, calculate in series power flow of a line after overload line tripping to confirm the parallel transmission section of overload line.

线路过载后，依序比较回路中线路与过载线路的潮流方向，以判定其是否属于过载线路的并行输电断面。

MAX1999EEI Pinout: 8- to 32-bit and 16- to 32-bit word packing options Programmable wait state options: 2 to 31 CCLK Digital audio interface includes six serial ports, two pre- cision clock generators, an input data port, three programmable timers and a signal routing unit Serial ports provide: Six dual data line serial ports that operate at up to 50 Mbits/s for a 200 MHz core on each data line each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair Left-justified sample pair and I2S support, programmable direction for up to 24 simultaneous receive or transmit channels using two I2S compatible stereo devices per serial port TDM support for telecommunications interfaces including 128 TDM channel support for telephony interfaces such as H.100/H.110 Up to 12 TDM stream support, each with 128 channels per frame Companding selection on a per channel basis in TDM mode Input data port provides an additional input path to the DSP core configurable as either eight channels of I2S or serial data or as seven channels plus a single 20-bit wide syn- chronous parallel data acquisition port Supports receive audio channel data in I2S, left-justified sample pair, or right-justified mode Signal routing unit provides configurable and flexible connections between all DAI components, six serial ports, an input data port, two precision clock generators, three timers, 10 interrupts, six flag inputs, six flag outputs, and 20 SRU I/O pins Serial peripheral interface Master or slave serial boot through SPI Full-duplex operation Master-slave mode multimaster support Open drain outputs Programmable baud rates, clock polarities, and phases 3 Muxed Flag/IRQ lines 1 Muxed Flag/Timer expired line ROM based security features: JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multi- plier/divider ratios JTAG background telemetry for enhanced emulation features IEEE 1149.1 JTAG standard test access port and on-chip emulation Dual voltage: 3.3 V I/O, 1.2 V core Available in 136-ball BGA and 144-lead LQFP packages Lead free packages are also available

MAX1999EEI引脚说明： 8 - 32位和16 - 32位字包装选择可编程等待状态的选择：2至31个CCLK数字音频接口包括6个串行端口，两个前643时钟发生器，输入数据端口， 3可编程定时器和一个信号路由单元串行端口提供：六双串口数据线，在高达50 Mbps的操作/为200兆赫的每个数据行每个人都有一个时钟，帧同步的核心秒，和两个数据可以作为任何一个接收器或发射器对左对齐和I2S配对样本的支持下，最多可同时接收或传送24个频道，每使用两个系列的I2S兼容立体声设备配置可编程方向线；港口的TDM通信接口，包括支持128个电话接口的TDM的渠道，如H.100/H.110支持多达12个的TDM流的支持下，每帧128个频道每个压缩扩展每通道的基础上选择在TDM模式输入数据端口提供了一个额外的输入路径的DSP核心配置为I2S或串行数据或7加一个20位宽的SYN -异步的并行数据采集接口通道或8通道；支持接收通道I2S音频数据，左对齐样本对，或右对齐模式信号路由单元组件之间提供所有戴配置和灵活的连接，6个串行端口，一个输入数据端口，两个精密时钟发生器，3个定时器，10个中断，六旗投入，产出6个旗，20曼谷南南区域股的I / O管脚串行外设接口的硕士或奴隶通过SPI串行启动全双工运作主从模式多主机支持开漏输出可编程波特率，时钟极性和第三期合并调制旗/ IRQ线路1合并调制旗/定时器过期线光盘的防伪特征：JTAG的访问与64位受保护的关键允许内存内存可分配给程序访问控制的限制下对敏感地区有一个代码锁相环/遥测分比率为背景的JTAG仿真功能增强的IEEE 1149.1 JTAG标准测试访问端口的软件和硬件多钳各种各样和片上仿真双电压：3.3六/输出，可在1.2 V核心136球BGA封装和144引脚LQFP封装无铅封装，也可

TDA4864 Pinout: 8- to 32-bit and 16- to 32-bit word packing options Programmable wait state options: 2 to 31 CCLK Digital audio interface includes six serial ports, two pre- cision clock generators, an input data port, three programmable timers and a signal routing unit Serial ports provide: Six dual data line serial ports that operate at up to 50 Mbits/s for a 200 MHz core on each data line each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair Left-justified sample pair and I2S support, programmable direction for up to 24 simultaneous receive or transmit channels using two I2S compatible stereo devices per serial port TDM support for telecommunications interfaces including 128 TDM channel support for telephony interfaces such as H.100/H.110 Up to 12 TDM stream support, each with 128 channels per frame Companding selection on a per channel basis in TDM mode Input data port provides an additional input path to the DSP core configurable as either eight channels of I2S or serial data or as seven channels plus a single 20-bit wide syn- chronous parallel data acquisition port Supports receive audio channel data in I2S, left-justified sample pair, or right-justified mode Signal routing unit provides configurable and flexible connections between all DAI components, six serial ports, an input data port, two precision clock generators, three timers, 10 interrupts, six flag inputs, six flag outputs, and 20 SRU I/O pins Serial peripheral interface Master or slave serial boot through SPI Full-duplex operation Master-slave mode multimaster support Open drain outputs Programmable baud rates, clock polarities, and phases 3 Muxed Flag/IRQ lines 1 Muxed Flag/Timer expired line ROM based security features: JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multi- plier/divider ratios JTAG background telemetry for enhanced emulation features IEEE 1149.1 JTAG standard test access port and on-chip emulation Dual voltage: 3.3 V I/O, 1.2 V core Available in 136-ball BGA and 144-lead LQFP packages Lead free packages are also available

TDA4864引脚说明： 8 - 32位和16 - 32位字包装选择可编程等待状态的选择：2至31个CCLK数字音频接口包括6个串行端口，两个前643时钟发生器，输入数据端口， 3可编程定时器和一个信号路由单元串行端口提供：六双串口数据线，在高达50 Mbps的操作/为200兆赫的每个数据行每个人都有一个时钟，帧同步的核心秒，和两个数据可以作为任何一个接收器或发射器对左对齐和I2S样本对支持，最多可同时接收或传送24个频道，每使用两个系列的I2S兼容立体声设备配置可编程方向线；港口的TDM通信接口，包括支持128个电话接口的TDM的渠道，如H.100/H.110支持多达12个的TDM流的支持下，每帧128个频道每个压缩扩展每通道的基础上选择在TDM模式输入数据端口提供了一个额外的输入路径的DSP核心配置为I2S或串行数据或7加一个20位宽的SYN -异步的并行数据采集接口通道或8通道；支持接收通道I2S音频数据，左对齐样本对，或右对齐模式信号路由单元组件之间提供所有戴配置和灵活的连接，6个串行端口，一个输入数据端口，两个精密时钟发生器，3个定时器，10个中断，六旗投入，产出6个旗，20曼谷南南区域股的I / O管脚串行外设接口的硕士或奴隶通过SPI串行启动全双工运作主从模式多主机支持开漏输出可编程波特率，时钟极性和第三期合并调制旗/ IRQ线路1合并调制旗/定时器过期线光盘的防伪特征：JTAG的访问与64位受保护的关键允许内存内存可分配给程序访问控制的限制下对敏感地区有一个代码锁相环/分比率背景遥测的JTAG仿真功能增强的IEEE 1149.1 JTAG标准测试访问端口软件和硬件多钳各种各样和片上仿真双电压：3.3六/输出，可在1.2 V核心136球BGA封装和144引脚LQFP封装无铅封装，也可

Taking the laser diode line generator as the light source, the parallel laser screen unit was formed by using aplanatic cylindrical Fresnel lens with long focal length. By splicing seamlessly with multiple parallel laser-screen units, the large area laser screen can he constructed.

以半导体激光线发生器为光源，用长焦距消球差的柱面菲涅耳透镜形成平行激光幕单元，通过多个平行激光幕单元的无缝拼接可形成大面积靶面。

WHEN A STRAIGHE LINE TURNS IN SPACE PARALLEL TO AN AXIS , IT GENERATES A CYLINDER . WHEN IT IS NOT PARALLEL , IT GENERATES A HYPERBOLID OF REVOLUTION OF ONE SHEET . A HALF-HYPERBOLOID IS THE THE IDEAL SHAPE FOR A BELL

这种柔和的平面在传说建筑中没有应用过，但是由于它具有良好的采光、传音和散重能力，所以高迪在柱子、柱头、屋顶，天窗和大钟中曾多次使用。

In his article entitled "On the manufacture of diffraction gratings and theoretical," the paper wrote,"If every inch with the same number of two engraved lines in contact with photographic copies of the state, the two grating The engraved lines are almost parallel will result in a set of parallel stripes, the direction of the two grating carved exterior angle between the line bisection, and their distance decreases with increasing inclination."

他在一篇题为"关于衍射光栅的制造和理论"的论文中写到"如果把每英寸具有同样数目的刻线的两个照相复制品处于接触状态，使两个光栅中的刻线几乎平行则就会产生一组平行的条纹，其方向将两个光栅刻线之间的外角二等分，而其距离随着倾角的减小而增大"。

After being connected with a resistor in series, the primary input end of a transformer is connected with the output end of the live wire and the output end of the null line in parallel, the secondary output end is connected with the two ends of the earth wire switch in parallel after being connected with another resistor in series, one end of a neon lamp in a photoelectric coupler is connected with the input end of the earth wire E and a secondary end of the transformer, the other end of the neon lamp is connected with the centers of the two resistors, one end of a light sensitive resistor in a photoelectric coupling switch is connected with the anode of an integrated circuit power in the creepage protector, the other end of the light sensitive resistor is connected with the anode of a diode, the cathode of the diode is connected with the triggering pole of the silicon-controlled rectifier in the creepage protector, the neon lamp and the light sensitive resistor are positioned into a dark box, and a small hole which avoids the light sensitive resistor is formed on the dark box.

防止地线触点未导通的全能安全插头，包括各带开关的地、零、相三线接线和由零序互感器、脱扣器、放大器、整流器、试验回路和可控硅组成的漏电保护器，变压器初级输入端串联电阻后并接在火线输出端和零线输出端，次级输出端与电阻串联后并联在地线开关两端，光耦内氖灯的一端与地线E输入端和变压器次级的一端连接，氖灯另一端与二电阻的中心连接，光电耦合开关内光敏电阻的一端与漏电保护器内的集成电路电源正极连接、光敏电阻的另一端与二极管的正极连接，二极管的负极与漏电保护器内的可控硅触发极连接，氖灯和光敏电阻置于暗箱中，暗箱上开一避开光敏电阻的小孔。

Bi-conversion UPSs operate in serial regulating work mode, on-line interactive UPSs in parallel regulating work mode, and DP300E circuits in serial-parallel regulating work mode which improve the performance of single-conversion and bi-conversion UPSs, and make themselves of high efficiency, stability and reliability.

双变换UPS工作于串联调整工作模式，在线互动式UPS工作于并联调整模式，而DP300E的电路则工作于串、并联联合调整的模式，提高了双变换和单变换UPS的性能，使之具有很高的效率、稳定性及可靠性。

This equipment applies some advanced techniques, including short net identical phase anti-parallel link rectification, resistor split resolving rectiformer, 3 inch thyristor parallel link, on-line current automatic periodic anti-direction, and automatic voltage regulating and current stabilizing.

该装置采用了短网同相逆并联整流，阻抗裂解式整流变压器，3in(7.62cm)晶闸管并联技术，在线电流自动周期反向和自动调压、稳流技术。

It was just a normal day of school

那只是上学的普通一天

Which is a very good reference in this issue.

这是一个在这个问题上很好的参考。