查询词典 output data

LT3468ES5-1 Pinout: 8-bit Resolution 1 Gsps Sampling Rate ADC Gain Adjust 2 GHz Full Power Input Bandwidth Fs = 1 Gsps, Fin = 20 MHz: C SINAD = 45 dB (7.4 Effective Bits) SFDR = 58 dBc Fs = 1 Gsps, Fin = 500 MHz: C SINAD = 44 dB (7.2 Effective Bits) SFDR = 56 dBc Fs = 1 Gsps, Fin = 1000 MHz (-3 dB Fs): C SINAD = 42 dB (7.0 Effective Bits) SFDR = 52 dBc 2 Tone IMD:-53 dBc (489 MHz and 490 MHz) at 1 Gsps DNL = 0.3 LSB INL = 0.7 LSB Low Bit Error Rate (10-13) at 1 Gsps Very Low Input Capacitance: 0.4 pF 500 mVpp Differential or Single-ended Analog Inputs Differential or Single-ended 50 ECL Compatible Clock Inputs ECL or LVDS/HSTL Output Compatibility Data Ready Output with Asynchronous Reset Gray or Binary Selectable Output Data; NRZ Output Mode Power Consumption: 3.4 W at TJ = 90 C Dual Power Supply: 5 V Radiation Tolerance Oriented Design 150 Krad (Si Measured

LT3468ES5-1引脚说明： 8位分辨率1 GSPS的采样速率ADC的增益调整2 GHz的全功率输入带宽= 1 GSPS的二恶英，翅= 20兆赫中：C的SINAD = 45分贝（7.4有效位）的SFDR = 58 dBc的二恶英= 1 GSP的，财务= 500兆赫中：C的SINAD = 44分贝（7.2有效位）的SFDR = 56 = 1 GSPS的dBc的外勤人员，财务= 1000兆赫（-3分贝财经事务）中：C的SINAD = 42分贝（7.0有效位）的SFDR = 52 dBc的2声调发展学院：-53 dBc的（489兆赫和1 GSPS的的DNL = 0.3的LSB的INL = 0.7 LSB的低误码率（10-13）在1 GSPS的非常低输入电容：0.4 pF的490兆赫）500 mVpp的差分或单端模拟输入差分或单端50Ω的ECL兼容的时钟输入的ECL或LVDS / HSTL输出兼容性数据与异步复位灰色或二进制可选的输出数据就绪输出； NRZ码输出模式下的功耗：3.4 W于温度Tj = 90 C双电源：5伏辐射性导向设计

The method includes steps: digital watermark technique is adopted to hide information of key data in not key data codes of compressed image; under protection of digital watermark, using protective backup for key data detects whether normal transmitted key data is correct or not so as to detect error code; carrying out cyclic mutual backup by using macro blocks in same positions in front and back macro block set; embedding coded motion vector in form of digital watermark to DCT transformation coefficient, and ensuring that video data are not influenced as best as one can; when error code occurs, if key data backup is correct, then the backup replaces former key data; otherwise, using mean value of key data in adjacent macro blocks within same frame to replace former key data approximately.

本发明中，采用数字水印技术在压缩图像的非关键数据编码中隐藏关键数据信息；通过数字水印保护下的关键数据保护备份来检测正常传输的关键数据是否正确，由此来检测传输误码；用前后宏块组中相同位置的宏块进行循环相互备份；对运动向量进行编码，然后以数字水印的形式嵌入到相对不重要的DCT变换系数中，同时保证视频数据尽量不受影响；在误码发生时，如果关键数据备份正确，则直接替代原关键数据，否则用同一帧内相邻宏块的关键数据的平均值近似替代原关键数据。

A method is provided for encoding and decoding a sequence of digital data, according to which a portion of the sequence of digital data corresponds to a data block that includes several data packets, at least two data packets per data block containing an identifier. The position of the data packet within the corresponding data block can be determined based on the identifier, and the data is encoded or decoded by taking into account the identifier.

本发明给出了一种用于对数字数据序列进行编码和解码的方法，其中该数字数据序列的一部分相当于一个数据块，其中该数据块包含多个数据包，其中每个数据块的至少两个数据包分别包含一个特征标记，其中根据该特征标记确定数据包在所属的数据块中的位置，以及其中在考虑该特征标记的情况下对数据进行编码或解码。

The method includes establishing one reverse mapping list comprising list items; reading the mapping data recorded in the data block state list item area to the list items during system initialization; checking reverse mapping list and finding the data block in Flash memory during reading some logic block; and writing the updated data into the empty data area of one new data block, writing the mapping data between the new logic block and the new data block into the state list item area and updating the mapping data of the corresponding list item in the reverse mapping list during writing some logic blcok.

包括：建立一个由表项组成的反向映射表，一个表项对应一个逻辑块；在系统初始化过程中，将数据块状态表项区中记录的映射信息，按逻辑块号与表项间的对应关系读取到各表项中；读取某逻辑块时，以其逻辑块号作为表项索引查找反向映射表，定位到表项，根据表项中记录的映射信息，在Flash存储器件中查找到数据块；写入某逻辑块时，将更新数据写入一新数据块的空白数据区中和将该逻辑块与新数据块间的映射信息写入状态表项区中，同时更新反向映射表相应表项的映射信息。

This invention discloses one data regroup method, which is based on the original independent and redundant RAID system high address to preserve one block disk space as regroup area and to repeat the following steps: a, determining the current regroup data low address and to regroup the data from high address to low address into new RAIN type of data; writing the regroup data from initial address into the new RAID type data; using the current regroup data of low address as the next regroup data high address as the next second initial address of the data.

本发明公开了一种数据重组方法，在原独立冗余磁盘阵列系统高地址侧尾部预留一块磁盘空间作为重组区域，将该预留重组区域的高地址作为写入数据的起始地址，并将原RAID系统中存有数据的高地址作为重组数据的起始高地址；数据重组完之前重复执行以下步骤：确定当前要重组数据的低地址，并将当前要重组数据高地址到低地址之间的数据重组为新RAID类型数据；将重组后的数据从写入数据的起始地址向低地址方向，顺序写入新RAID系统中；当前要重组数据低地址的邻接低地址作为下次要重组数据的高地址，当前写入数据低地址的邻接低地址作为下次写入数据的起始地址。

The main features of this paper is: nothing to do with the platform, this system can be compatible with the majority of software and hardware used by the platform, as well as various database platform, shielding the differences of hardware and software platform such as network, operating systems, databases, application systems and so on, so that enterprises and institutions could achieve seamless, transparent data exchange through data exchange system; Java technology used to develop the system transplantability; using data exchange center to achieve centralized data processing, different data format conversion, increased system scalability; from data transmission, authentication, access control, encryption and more news content log-class areas enhanced data exchange system security; using DES and RSA algorithm , increased the confidentiality of data transmission; create WrapperTimer category achieved data transmission timing implementation and reduce the dependence on artificial.

设计的系统与平台无关，能兼容企业所用的大多数软硬件平台，以及各种数据库平台，屏蔽网络、操作系统、数据库、应用系统等软硬平台的差异，使企事业单位通过数据交换系统实现无缝的、透明的交换数据；采用数据交换中心来实现数据的集中处理、不同数据格式的转换，增加了系统的可扩展性；从数据传输、身份认证、权限控制、消息内容加密和多级日志等多方面增强数据交换系统的安全性；用DES和RSA算法对XML文件或XML文件中的元素进行加密，增加传输数据的保密性；创建WrapperTimer类实现了数据传输的定时执行，降低了对人工的依赖性。

MAX1999EEI Pinout: 8- to 32-bit and 16- to 32-bit word packing options Programmable wait state options: 2 to 31 CCLK Digital audio interface includes six serial ports, two pre- cision clock generators, an input data port, three programmable timers and a signal routing unit Serial ports provide: Six dual data line serial ports that operate at up to 50 Mbits/s for a 200 MHz core on each data line each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair Left-justified sample pair and I2S support, programmable direction for up to 24 simultaneous receive or transmit channels using two I2S compatible stereo devices per serial port TDM support for telecommunications interfaces including 128 TDM channel support for telephony interfaces such as H.100/H.110 Up to 12 TDM stream support, each with 128 channels per frame Companding selection on a per channel basis in TDM mode Input data port provides an additional input path to the DSP core configurable as either eight channels of I2S or serial data or as seven channels plus a single 20-bit wide syn- chronous parallel data acquisition port Supports receive audio channel data in I2S, left-justified sample pair, or right-justified mode Signal routing unit provides configurable and flexible connections between all DAI components, six serial ports, an input data port, two precision clock generators, three timers, 10 interrupts, six flag inputs, six flag outputs, and 20 SRU I/O pins Serial peripheral interface Master or slave serial boot through SPI Full-duplex operation Master-slave mode multimaster support Open drain outputs Programmable baud rates, clock polarities, and phases 3 Muxed Flag/IRQ lines 1 Muxed Flag/Timer expired line ROM based security features: JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multi- plier/divider ratios JTAG background telemetry for enhanced emulation features IEEE 1149.1 JTAG standard test access port and on-chip emulation Dual voltage: 3.3 V I/O, 1.2 V core Available in 136-ball BGA and 144-lead LQFP packages Lead free packages are also available

MAX1999EEI引脚说明： 8 - 32位和16 - 32位字包装选择可编程等待状态的选择：2至31个CCLK数字音频接口包括6个串行端口，两个前643时钟发生器，输入数据端口， 3可编程定时器和一个信号路由单元串行端口提供：六双串口数据线，在高达50 Mbps的操作/为200兆赫的每个数据行每个人都有一个时钟，帧同步的核心秒，和两个数据可以作为任何一个接收器或发射器对左对齐和I2S配对样本的支持下，最多可同时接收或传送24个频道，每使用两个系列的I2S兼容立体声设备配置可编程方向线；港口的TDM通信接口，包括支持128个电话接口的TDM的渠道，如H.100/H.110支持多达12个的TDM流的支持下，每帧128个频道每个压缩扩展每通道的基础上选择在TDM模式输入数据端口提供了一个额外的输入路径的DSP核心配置为I2S或串行数据或7加一个20位宽的SYN -异步的并行数据采集接口通道或8通道；支持接收通道I2S音频数据，左对齐样本对，或右对齐模式信号路由单元组件之间提供所有戴配置和灵活的连接，6个串行端口，一个输入数据端口，两个精密时钟发生器，3个定时器，10个中断，六旗投入，产出6个旗，20曼谷南南区域股的I / O管脚串行外设接口的硕士或奴隶通过SPI串行启动全双工运作主从模式多主机支持开漏输出可编程波特率，时钟极性和第三期合并调制旗/ IRQ线路1合并调制旗/定时器过期线光盘的防伪特征：JTAG的访问与64位受保护的关键允许内存内存可分配给程序访问控制的限制下对敏感地区有一个代码锁相环/遥测分比率为背景的JTAG仿真功能增强的IEEE 1149.1 JTAG标准测试访问端口的软件和硬件多钳各种各样和片上仿真双电压：3.3六/输出，可在1.2 V核心136球BGA封装和144引脚LQFP封装无铅封装，也可

TDA4864 Pinout: 8- to 32-bit and 16- to 32-bit word packing options Programmable wait state options: 2 to 31 CCLK Digital audio interface includes six serial ports, two pre- cision clock generators, an input data port, three programmable timers and a signal routing unit Serial ports provide: Six dual data line serial ports that operate at up to 50 Mbits/s for a 200 MHz core on each data line each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair Left-justified sample pair and I2S support, programmable direction for up to 24 simultaneous receive or transmit channels using two I2S compatible stereo devices per serial port TDM support for telecommunications interfaces including 128 TDM channel support for telephony interfaces such as H.100/H.110 Up to 12 TDM stream support, each with 128 channels per frame Companding selection on a per channel basis in TDM mode Input data port provides an additional input path to the DSP core configurable as either eight channels of I2S or serial data or as seven channels plus a single 20-bit wide syn- chronous parallel data acquisition port Supports receive audio channel data in I2S, left-justified sample pair, or right-justified mode Signal routing unit provides configurable and flexible connections between all DAI components, six serial ports, an input data port, two precision clock generators, three timers, 10 interrupts, six flag inputs, six flag outputs, and 20 SRU I/O pins Serial peripheral interface Master or slave serial boot through SPI Full-duplex operation Master-slave mode multimaster support Open drain outputs Programmable baud rates, clock polarities, and phases 3 Muxed Flag/IRQ lines 1 Muxed Flag/Timer expired line ROM based security features: JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multi- plier/divider ratios JTAG background telemetry for enhanced emulation features IEEE 1149.1 JTAG standard test access port and on-chip emulation Dual voltage: 3.3 V I/O, 1.2 V core Available in 136-ball BGA and 144-lead LQFP packages Lead free packages are also available

TDA4864引脚说明： 8 - 32位和16 - 32位字包装选择可编程等待状态的选择：2至31个CCLK数字音频接口包括6个串行端口，两个前643时钟发生器，输入数据端口， 3可编程定时器和一个信号路由单元串行端口提供：六双串口数据线，在高达50 Mbps的操作/为200兆赫的每个数据行每个人都有一个时钟，帧同步的核心秒，和两个数据可以作为任何一个接收器或发射器对左对齐和I2S样本对支持，最多可同时接收或传送24个频道，每使用两个系列的I2S兼容立体声设备配置可编程方向线；港口的TDM通信接口，包括支持128个电话接口的TDM的渠道，如H.100/H.110支持多达12个的TDM流的支持下，每帧128个频道每个压缩扩展每通道的基础上选择在TDM模式输入数据端口提供了一个额外的输入路径的DSP核心配置为I2S或串行数据或7加一个20位宽的SYN -异步的并行数据采集接口通道或8通道；支持接收通道I2S音频数据，左对齐样本对，或右对齐模式信号路由单元组件之间提供所有戴配置和灵活的连接，6个串行端口，一个输入数据端口，两个精密时钟发生器，3个定时器，10个中断，六旗投入，产出6个旗，20曼谷南南区域股的I / O管脚串行外设接口的硕士或奴隶通过SPI串行启动全双工运作主从模式多主机支持开漏输出可编程波特率，时钟极性和第三期合并调制旗/ IRQ线路1合并调制旗/定时器过期线光盘的防伪特征：JTAG的访问与64位受保护的关键允许内存内存可分配给程序访问控制的限制下对敏感地区有一个代码锁相环/分比率背景遥测的JTAG仿真功能增强的IEEE 1149.1 JTAG标准测试访问端口软件和硬件多钳各种各样和片上仿真双电压：3.3六/输出，可在1.2 V核心136球BGA封装和144引脚LQFP封装无铅封装，也可

Output of 12 million and automobile semi-axle output of 650 thousand, which separately accounted for 14% and 27% of national output, among which, the output of coach gear box has accounted for 80% of national output.

綦江县境内拥有以綦江齿轮厂为主体，綦江齿轮传动公司为核心，綦齿汽车零部件公司等企业在内的綦齿集团以及长风齿轮等6家骨干和150余个齿轮机械制造加工企业。2006年完成汽车齿轮（变速器齿轮、驱动桥齿轮、轮边减速器系统齿轮、同步器等）产量1200万件，汽车半轴65万件，分别占全国产量的14%和27%，客车变速箱已经占全国的80%。

The probability model of Extensive Generalized Self-shrinking Generator is constructed. The output time sequences and the output sequences are analyzed: the output time sequences are proved as a homogeneous Markov chain, and the output sequences are independent and identically uniform distributed. The coincidence between the output sequences and some correlation sequences in this generator is given.

然后，建立了泛广义自缩减生成器的概率模型，分析了该生成器的输出时间序列及输出序列的性质，得到了生成器的输出时间序列是一个齐次马氏链，输出序列是独立同均匀分布的随机变量序列，还得到了输出序列与生成器中一些相关序列的符合率。

When this condition occurs, inbound replication with the source partner is stopped on the destination domain controller and event ID 2042 is logged in the Directory Services event log.

计算机密码学是研究计算机信息加密、解密及其变换的科学，是数学和计算机的交义学科，也是一门新兴的学科。

Instructions: click on the thumbnails to see a larger image, then use the left-right arrow keys to scroll through the slideshow.

使用说明：滑鼠点在小图上即可放大观赏。开启后键盘左右键可用来换照片。