查询词典 media control interface

MAX1999EEI Pinout: 8- to 32-bit and 16- to 32-bit word packing options Programmable wait state options: 2 to 31 CCLK Digital audio interface includes six serial ports, two pre- cision clock generators, an input data port, three programmable timers and a signal routing unit Serial ports provide: Six dual data line serial ports that operate at up to 50 Mbits/s for a 200 MHz core on each data line each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair Left-justified sample pair and I2S support, programmable direction for up to 24 simultaneous receive or transmit channels using two I2S compatible stereo devices per serial port TDM support for telecommunications interfaces including 128 TDM channel support for telephony interfaces such as H.100/H.110 Up to 12 TDM stream support, each with 128 channels per frame Companding selection on a per channel basis in TDM mode Input data port provides an additional input path to the DSP core configurable as either eight channels of I2S or serial data or as seven channels plus a single 20-bit wide syn- chronous parallel data acquisition port Supports receive audio channel data in I2S, left-justified sample pair, or right-justified mode Signal routing unit provides configurable and flexible connections between all DAI components, six serial ports, an input data port, two precision clock generators, three timers, 10 interrupts, six flag inputs, six flag outputs, and 20 SRU I/O pins Serial peripheral interface Master or slave serial boot through SPI Full-duplex operation Master-slave mode multimaster support Open drain outputs Programmable baud rates, clock polarities, and phases 3 Muxed Flag/IRQ lines 1 Muxed Flag/Timer expired line ROM based security features: JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multi- plier/divider ratios JTAG background telemetry for enhanced emulation features IEEE 1149.1 JTAG standard test access port and on-chip emulation Dual voltage: 3.3 V I/O, 1.2 V core Available in 136-ball BGA and 144-lead LQFP packages Lead free packages are also available

MAX1999EEI引脚说明： 8 - 32位和16 - 32位字包装选择可编程等待状态的选择：2至31个CCLK数字音频接口包括6个串行端口，两个前643时钟发生器，输入数据端口， 3可编程定时器和一个信号路由单元串行端口提供：六双串口数据线，在高达50 Mbps的操作/为200兆赫的每个数据行每个人都有一个时钟，帧同步的核心秒，和两个数据可以作为任何一个接收器或发射器对左对齐和I2S配对样本的支持下，最多可同时接收或传送24个频道，每使用两个系列的I2S兼容立体声设备配置可编程方向线；港口的TDM通信接口，包括支持128个电话接口的TDM的渠道，如H.100/H.110支持多达12个的TDM流的支持下，每帧128个频道每个压缩扩展每通道的基础上选择在TDM模式输入数据端口提供了一个额外的输入路径的DSP核心配置为I2S或串行数据或7加一个20位宽的SYN -异步的并行数据采集接口通道或8通道；支持接收通道I2S音频数据，左对齐样本对，或右对齐模式信号路由单元组件之间提供所有戴配置和灵活的连接，6个串行端口，一个输入数据端口，两个精密时钟发生器，3个定时器，10个中断，六旗投入，产出6个旗，20曼谷南南区域股的I / O管脚串行外设接口的硕士或奴隶通过SPI串行启动全双工运作主从模式多主机支持开漏输出可编程波特率，时钟极性和第三期合并调制旗/ IRQ线路1合并调制旗/定时器过期线光盘的防伪特征：JTAG的访问与64位受保护的关键允许内存内存可分配给程序访问控制的限制下对敏感地区有一个代码锁相环/遥测分比率为背景的JTAG仿真功能增强的IEEE 1149.1 JTAG标准测试访问端口的软件和硬件多钳各种各样和片上仿真双电压：3.3六/输出，可在1.2 V核心136球BGA封装和144引脚LQFP封装无铅封装，也可

TDA4864 Pinout: 8- to 32-bit and 16- to 32-bit word packing options Programmable wait state options: 2 to 31 CCLK Digital audio interface includes six serial ports, two pre- cision clock generators, an input data port, three programmable timers and a signal routing unit Serial ports provide: Six dual data line serial ports that operate at up to 50 Mbits/s for a 200 MHz core on each data line each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair Left-justified sample pair and I2S support, programmable direction for up to 24 simultaneous receive or transmit channels using two I2S compatible stereo devices per serial port TDM support for telecommunications interfaces including 128 TDM channel support for telephony interfaces such as H.100/H.110 Up to 12 TDM stream support, each with 128 channels per frame Companding selection on a per channel basis in TDM mode Input data port provides an additional input path to the DSP core configurable as either eight channels of I2S or serial data or as seven channels plus a single 20-bit wide syn- chronous parallel data acquisition port Supports receive audio channel data in I2S, left-justified sample pair, or right-justified mode Signal routing unit provides configurable and flexible connections between all DAI components, six serial ports, an input data port, two precision clock generators, three timers, 10 interrupts, six flag inputs, six flag outputs, and 20 SRU I/O pins Serial peripheral interface Master or slave serial boot through SPI Full-duplex operation Master-slave mode multimaster support Open drain outputs Programmable baud rates, clock polarities, and phases 3 Muxed Flag/IRQ lines 1 Muxed Flag/Timer expired line ROM based security features: JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multi- plier/divider ratios JTAG background telemetry for enhanced emulation features IEEE 1149.1 JTAG standard test access port and on-chip emulation Dual voltage: 3.3 V I/O, 1.2 V core Available in 136-ball BGA and 144-lead LQFP packages Lead free packages are also available

TDA4864引脚说明： 8 - 32位和16 - 32位字包装选择可编程等待状态的选择：2至31个CCLK数字音频接口包括6个串行端口，两个前643时钟发生器，输入数据端口， 3可编程定时器和一个信号路由单元串行端口提供：六双串口数据线，在高达50 Mbps的操作/为200兆赫的每个数据行每个人都有一个时钟，帧同步的核心秒，和两个数据可以作为任何一个接收器或发射器对左对齐和I2S样本对支持，最多可同时接收或传送24个频道，每使用两个系列的I2S兼容立体声设备配置可编程方向线；港口的TDM通信接口，包括支持128个电话接口的TDM的渠道，如H.100/H.110支持多达12个的TDM流的支持下，每帧128个频道每个压缩扩展每通道的基础上选择在TDM模式输入数据端口提供了一个额外的输入路径的DSP核心配置为I2S或串行数据或7加一个20位宽的SYN -异步的并行数据采集接口通道或8通道；支持接收通道I2S音频数据，左对齐样本对，或右对齐模式信号路由单元组件之间提供所有戴配置和灵活的连接，6个串行端口，一个输入数据端口，两个精密时钟发生器，3个定时器，10个中断，六旗投入，产出6个旗，20曼谷南南区域股的I / O管脚串行外设接口的硕士或奴隶通过SPI串行启动全双工运作主从模式多主机支持开漏输出可编程波特率，时钟极性和第三期合并调制旗/ IRQ线路1合并调制旗/定时器过期线光盘的防伪特征：JTAG的访问与64位受保护的关键允许内存内存可分配给程序访问控制的限制下对敏感地区有一个代码锁相环/分比率背景遥测的JTAG仿真功能增强的IEEE 1149.1 JTAG标准测试访问端口软件和硬件多钳各种各样和片上仿真双电压：3.3六/输出，可在1.2 V核心136球BGA封装和144引脚LQFP封装无铅封装，也可

Based on the analysis of the concept of the man-machine interface of toy, the display device and control device during the process of the man - machine interface design of toy was discussed.

在对玩具人机界面概念解析的基础上，就玩具人机界面设计过程中的各项显示装置、控制装置逐一展开讨论。

On CHE programming, the higher coupling ratio of control-gate makes the higher electrical field across TOX in Si than Ge. Also because of the continuity of displacement vector, the higher permittivity of Ge would cause the lower electrical field at interface. We get the higher gate current in Si than Ge. On CFN programming, the higher CT in Ge would show the higher electrical field across TOX. However, the parameters of F-N tunneling are calculated and showing the gate current in Si is larger than Ge. On the same mechanism of F-N tunneling erasing, the parameters also show the higher electrical filed of Si would cause the higher erasing speed. The continuity of displacement vector also explains the higher electrical field at interface for F-N tunneling programming/erasing.

从通道热电子穿隧写入的模拟结果发现，由於控制闸极耦合电容的影响，加上电位移向量在半导体-氧化层界面连续的观念，拥有较高介电常数的锗反而得到较小的等效电场，决定了穿隧电流反倒是不如矽基板；在F-N穿隧写入的模拟中，即便锗基板拥有较大的总耦合电容，使得在浮闸的耦合电压大於矽基板，但仍旧是半导体-氧化层界面的电场扮演了穿隧电流的决定性因素，得到的结果仍旧是矽基板的写入速度高於锗基板；在F-N抹除的模拟中，运用与F-N写入相同的数学模型，仍旧看见在锗基板上未能得到速度上的改善，同时用数学的计算展示了合理的解释。

CD-drive controller is a single chip microcomputer to control the CD-ROM player CD, control panel, online call CDROM controller, CDROM controller is through the IDE interface to control the CD-ROM drive.

光驱控制器是一款用单片机来控制光驱播放CD的控制板，网上称它为CDROM控制器，CDROM控制器是通过IDE接口来控制光驱的。

Key words: distributed control system; sequence control system; low voltage motor; interface technology; control

关键词］分散控制系统；顺序控制系统；低压电机；接口技术；控制

The measuring system is comprised of three layers of components: an electrochemical control layer, a fluidic control layer, and a control interface layer.

所观察到的有效振动模式主要是苯环平面上对称的运动，和苯胺上所观察的结果相互一致。

A two-layered structure of control plane without multicast routing protocols is implemented by overlaying novel service control plane over the existing routing control plane to support multicast state aggregate. The interface between the two planes is formulated to support the interaction and cooperation.

针对这些问题，提出了基于汇聚方法的新型MPLS服务质量组播体系结构，提出在现有的路由控制平面上叠加一层面向IP组播服务的控制平面，取代组播路由协议并支持组播聚集，形成2层控制平面结构。

For the characteristics of voile cleaning machine in textile producing, a new control system based on CAN fieldbus is presented in this paper, The principle of the system is introduced, The interface of the network and the communication protocol of the system are discussed in detail, The design of control software is also analyzed, the main program of communication is given. For CAN network communication of master and slave station,the system works reliably, and the voile cleaning is controlled intelligently. It is an advanced control technology. which is verified in practice .

针对纺织生产过程中清纱机的工作特点，提出了一种基于CAN总线技术的控制系统设计方法，分析了系统的工作原理、网络拓扑结构及其硬件构成，详细阐述了CAN总线的网络接口方法和系统通信协议，讨论了控制软件的设计，给出了CAN网络的主要通信程序，由于这种系统的主、从站之间采用CAN网络通信，实现了对清纱工程的智能控制，系统具有运行可靠、性能价格比高的特点，实践证明这是一种先进的控制技术，具有较大的推广意义。

The main related design are on the following: Using RS232 to realize the target of communication links between host computer and target machines, and to test the PC serial; to make target machine startup disk; to design the Interface of target Machine ; to develop a device driver program module against remote data acquisition and control system ADAM5000 using the technical framework of xPC; and to realize Data Acquisition and controlling according to using ADAM5000 device driver program module against an actual water level in the block diagram of PID processing control system, the generation of real-time control procedures at the scene Debugging was expected to controlling effect.

本课题主要做了以下相关设计：利用RS232实现宿主机与目标机之间通信连接及对PC机串口的检测、制作目标机启动盘、设计目标机界面及在xPC技术框架下针对远端数据采集与控制系统ADAM5000开发了设备驱动程序模块，并以一个实际水箱液位为背景，在已有的PID液位过程控制系统算法框图中应用该设备驱动程序模块实现对现场设备的数据采集和控制，所生成的实时控制程序在现场调试中获得了预期的控制效果。

I'm not an actor. I'm a professor of paleontology.

我不是演员，我是古生物学教授

Spider Network Web site that is a very image of the name.

网络蜘蛛即Web Spider，是一个非常形象的名字。