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logic level相关的网络例句

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与 logic level 相关的网络例句 [注:此内容来源于网络,仅供参考]

The A data is latched if LE is low and clock is held at a high or low logic level.

在一个数据锁存如果LE是低,时钟是在高或低的逻辑电平举行。

Similarly, the output terminals and the corresponding output logic level are Q and .

同样的,输出端子和相应的输出逻辑电平为Q and 。

Thus, S=1 indicates that a voltage corresponding to logic level 1 is normally present at terminal S.

因此,S=1,表示端子S逻辑值为1的电平。

Modeling and controlling of the Discrete Event Dynamic Systems on the logic level are very significant aspects in the research of DEDS.

在离散事件动态系统的研究中,逻辑层次的建模与控制是一个很重要的方面。

When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level.

当LEAB低,如果一个数据锁存CLKAB是在高或低的逻辑电平举行。

VL is set to Logic Level for Device Off operation.

VL被设置为逻辑电平开关操作装置。

Similarly, the output terminals and the corresponding output logic level are Q and Q .

通过这种表示方式,我们已经明显考虑这样的事实:在通常的运算中,输出的逻辑电平是互补的。

The user can supply interface hardware to use this logic level signal

用户可以通过硬件接口,应用

These dual P-Channel logic level enhancement mode MOSFET are produced using Fairchild Semiconductors especially tailored to minimize on-state resistance.

这些双P沟道MOSFET的逻辑水平的提高模式是利用快捷半导体公司特别定制,以减少对国家的阻力。

In addition, it implements various mechanisms presented in the dissertation, and the logic level integration of heterogenous knowledge models as well as some extensional mechanisms, used in reasoning inspection, verification and modification on the consistency and perfectiveness of description logics-based models.

为了检验上述理论研究,论文设计了基于KML的智能知识建模原型系统CAKE,系统提供RPC/Web/Web服务三种模式,并实现论文提出的各种机制以及异构知识模型的逻辑级集成和基于描述逻辑的模型一致性和完备性推理检查、校验与修正等扩充机制。

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