查询词典 jitter

The third, fifth and seventh harmonics were selected to calculate the pulse width jitter, and the corresponding product of pulse width and angular frequency, 7W, were 1.305, 2.175 and 3.045, respectively. With 25 kHz～5 MHz integration limits, the pulse width jitter was obtained to be 3.08ps.

选择脉冲重复频率的三次、五次和七次谐波的功率谱进行分析，三个谐波级次对应的脉冲宽度角频率积Tω分别为1.305，2.175和3.045，在25 kHz～5 MHz偏移频率范围内，得到的脉冲宽度抖动为3.08ps。

Fully Integrated Clock Recovery and Data Retiming Power Dissipation: 260mW with +3.3V Supply Clock Jitter Generation: 5mUIRMS Exceeds ANSI, ITU, and Bellcore SDH/SONET Jitter Specifications Differential Input Range: 50mVP-P to 1.6VP-P Single +3.3V Power Supply PLL Fast Track Mode Available Clock Output Can Be Disabled Input Data Rate: 2.488Gbps or 2.67Gbps Selectable Output Amplitude Tolerates 2000 Consecutive Identical Digits Loss-of-Lock Indicator Differential CML Data and Clock Outputs Operating Temperature Range:-40C to +85C

1第1页，本页显示记录1-5，共5条记录分1页显示完全集成的时钟恢复和数据重定时功耗：+3.3 V电源与时钟抖动产生：5mUIRMS超越美国ANSI，ITU和Bellcore实验室的SDH / SONET抖动规格差分输入范围：50mVP磷260mW至1.6VP - P的单+3.3 V供电锁相环快车道时钟输出模式下可用可以禁用输入数据速率：2.488Gbps或2.67Gbps可选输出振幅2000年连续容忍同位数丢失锁指示灯差分CML数据和时钟输出工作温度范围：-40℃至+85

The jitter mainly includes the jitter caused by transmitting of Line and the jitter occurred by equipments of compound connecter.

抖动、漂移是数字信号中所存在的相位噪声，抖动主要包括线路传输系统引起的抖动和复接器设备引起的抖动。

On the basis of the old model of ADC input clock jitter and signal, a formula functioned with ADC input clock jitter and ADC output code cumulative probability distribution function was deduced.

在已有的利用ADC采样研究时钟抖动基本模型的基础上，提出了利用ADC的输出码密度测量时钟抖动的修正模型。

Then, in order to trade off between the cost and performance of super-fine phase when realizing the low-jitter low-power high-performance frequency synthesizer for Ethernet application, a novel dynamic voltage-mode phase interpolator with 8-stage differential ring VCO has been provided satisfying the requirement of transmitter and receiver simultaneously. The chip has been implemented in SMIC 0.18-um standard CMOS process and achieved an RMS jitter of 11ps with the crystal oscillator reference RMS jitter of 16ps.

接着，在实现以太网低抖动低功耗高性能的频率综合器设计中，为了有效解决超精细相位性能与成本的矛盾，提出一种新颖的动态电压模相位内插电路，与8级环振VCO相配合，为系统同时满足发送与接收需求起到至关重要的作用。

In order to measure jitter of gain-switched laser precisely, we analyze theoretically the math model and measurement principle of harmonic spectrum analysis used to measure laser pulse jitter.

为了能够精确测量增益开关激光脉冲的抖动，应用傅里叶变换和自相关函数，理论分析了谐波频谱分析法测量激光脉冲抖动的数学模型、测量原理，修正了David A。

Because the length and fluctuation of queue affect network delay and jitter directly, the key point of how to control delay and jitter is to make use of effective method to control the queue length and degrade the queue fluctuation level.

队列的长度及其变化是影响网络的延时和抖动的重要因素，使用有效的方法对队列的长度进行控制并降低队列长度的变化幅度和范围，是控制延时和抖动问题的关键。

It shows that the performance degradation owing to timing jitter is mainly decided by the auto-correlation of the transmitted monocycle and the serious degree of the jitter.

结果表明，系统的抗时间抖动性能主要取决于单脉冲信号的自相关特性以及引入时间抖动的严重程度。

Key words: communication technology; jitter generator; equivalent noise voltage model; jitter; field programmable gate arrayFPGA

关键 词：通信技术；抖动发生器；等效噪声电压模型；抖动；现场可编程门阵列

Jitter transfer refers to the portion of jitter allowed to transfer from input to output of the CDR, and jitter generation is that produced by the CDR itself.

抖动转移是指抖动部分允许从输入转移到输出的CDR，并抖动是由自己制作的CDR。

Chrysanthemum of 10 thousand birthday is lax to edaphic requirement, with the arenaceous qualitative loam with fecund, good drainage had better.

万寿菊对土壤要求不严，以肥沃。排水良好的砂质壤土为好。

He unstepped the mast and furled the sail and tied it.

他拔下桅杆，把帆卷起，系住。