查询词典 interfaces

Moreover, different viscoelasticity characteristics at different interfaces for PHPAM solution were also found. Among those three interfaces were experimented, and the order of the numerical value of viscoelasticity from large to small is PHPAM/air interface, PHPAM/dodecane interface and PHPAM/crude oil interface.

聚合物溶液与不同物质所形成的界面具有不同的粘弹性特征，与空气、正十二烷、原油所形成界面的界面扩张粘弹模量E的大小次序为E空气＞E正十二烷＞E原油，即E随着两相密度差的减小而减小。

By measuring pressure induced by dynamiting which located various positions of the circular shell, the localizational effect of impact force on the circular shell is disclosed. Also, PVDF piezofilms are used to determine accurate time while projectile contacting target, accurate time while two interfaces of the target contacting at a initial distance of 5, and the contacting pressure between the two interfaces when the projectile is in 500m/s to lOOOm/s.

通过对化爆模拟加载试验中柱壳不同角度压力的监测，揭示了化爆模拟产生的压力局域化效应，为进一步模拟设计提出研究的方向；采用PVDF压电薄膜来监测弹靶碰撞的时刻、细小间隙的闭合时间以及由此产生的压力变化，通过对PVDF压力计测试结果分析以及和数值模拟结果的比较，获得规律性的认识，为进一步的应用提供了技术支持。

The BoundFields and CheckBoxFields used by the GridView and DetailsView controls simplify the process of modifying data due to their ability to render read-only, editable, and insertable interfaces. These interfaces can be rendered without the need for adding any additional declarative markup or code.

GridView和DetailsView控件通过绑定列和CheckBox列，可以简化数据编辑界面制作，呈现只读，编辑和新增界面，我们不需要增加元素标记或编写任何额外代码就可以得到这些界面。

If a switch can pass cells among all its interfaces at the full r ate of all interfaces, it is described as nonblocking.

如果交换机可以在所有接口上以全速率将信元发送至所有接口，它就是非阻塞的。

The composition theorem based on the nonsymmetrical interfaces was proved, in terms of which any two components interacting by harmonic interfaces could be combined into a single component.

第二，系统地建立了构件与接口、接口与接口的关系理论，明确了接口&和谐&交互的条件及构件&提供&接口的含义。

A sample is put on the table which is processed into a inclined plane on the filmed plane, and two interfaces of a film are focalized, then the thickness is read out that is a difference between the heights of two interfaces of a film.

将实验样品的覆膜面打磨成斜面后平放在金相显微镜样品台上，分别对膜层的两个界面对焦，从对焦旋钮上读出两焦面的高度差即为膜层的厚度。

On the other hand, T -type twin and α〓 laths were preferentially formed at these nonequilibrium interfaces. The lath formation process involves complex transformations of the interfacial dislocation core and can be activated preferentially under concentrated stress fields at these interlamellar interfaces.

其二，热形变Ti-45Al-8Nb合金片层结构中，由于偏离严格取向关系的α〓/γ，γ/γ〓片层片层界面上具有较大的应力集中，外应力将优先在这些α〓/γ片层界面上诱导形成T型孪生位错，从而形成横过γ片层的T型孪晶。

At the same time,a tension stress is applied on theγ′phase interfaces along the direction parallel to the stress axis,which results in the lattice expansion ofγ′phase to trap the Al,Ta atoms with the bigger radius.This brings out the accumulation of the solute atoms to form the N-type rafted structure.Al,Ta atoms with bigger radius diffuse to the {100} plane to form the linked bond of the heterogeneous atoms and the stable stacking mode,this is a main reason of promoting the transformation ofγ′phase into the N-type rafted structure.And the change of the strain energy density in different interfaces of the cubical-likeγ′phase is thought to be the driving force of the elements diffusion and theγ′phase directional growth during creep.

拉伸蠕变期间，类立方γ\'相中与施加应力轴垂直的界面受水平切应力，使晶格收缩可排斥较大半径的Al、Ta原子；与应力轴平行的界面受拉伸张应力，使晶格扩张可诱捕较大半径的Al、Ta原子，由此引起的原子偏聚形成γ\'相是自由能降低的过程；其中，较大半径的Al、Ta原子扩散迁移至{100}晶面，形成异类原子结合键及稳定的堆垛方式，是促使γ\'相形成N-型筏状结构的主要原因；而γ\'相不同界面的应变能密度变化是元素扩散及γ\'相定向粗化的驱动力。

MAX1999EEI Pinout: 8- to 32-bit and 16- to 32-bit word packing options Programmable wait state options: 2 to 31 CCLK Digital audio interface includes six serial ports, two pre- cision clock generators, an input data port, three programmable timers and a signal routing unit Serial ports provide: Six dual data line serial ports that operate at up to 50 Mbits/s for a 200 MHz core on each data line each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair Left-justified sample pair and I2S support, programmable direction for up to 24 simultaneous receive or transmit channels using two I2S compatible stereo devices per serial port TDM support for telecommunications interfaces including 128 TDM channel support for telephony interfaces such as H.100/H.110 Up to 12 TDM stream support, each with 128 channels per frame Companding selection on a per channel basis in TDM mode Input data port provides an additional input path to the DSP core configurable as either eight channels of I2S or serial data or as seven channels plus a single 20-bit wide syn- chronous parallel data acquisition port Supports receive audio channel data in I2S, left-justified sample pair, or right-justified mode Signal routing unit provides configurable and flexible connections between all DAI components, six serial ports, an input data port, two precision clock generators, three timers, 10 interrupts, six flag inputs, six flag outputs, and 20 SRU I/O pins Serial peripheral interface Master or slave serial boot through SPI Full-duplex operation Master-slave mode multimaster support Open drain outputs Programmable baud rates, clock polarities, and phases 3 Muxed Flag/IRQ lines 1 Muxed Flag/Timer expired line ROM based security features: JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multi- plier/divider ratios JTAG background telemetry for enhanced emulation features IEEE 1149.1 JTAG standard test access port and on-chip emulation Dual voltage: 3.3 V I/O, 1.2 V core Available in 136-ball BGA and 144-lead LQFP packages Lead free packages are also available

MAX1999EEI引脚说明： 8 - 32位和16 - 32位字包装选择可编程等待状态的选择：2至31个CCLK数字音频接口包括6个串行端口，两个前643时钟发生器，输入数据端口， 3可编程定时器和一个信号路由单元串行端口提供：六双串口数据线，在高达50 Mbps的操作/为200兆赫的每个数据行每个人都有一个时钟，帧同步的核心秒，和两个数据可以作为任何一个接收器或发射器对左对齐和I2S配对样本的支持下，最多可同时接收或传送24个频道，每使用两个系列的I2S兼容立体声设备配置可编程方向线；港口的TDM通信接口，包括支持128个电话接口的TDM的渠道，如H.100/H.110支持多达12个的TDM流的支持下，每帧128个频道每个压缩扩展每通道的基础上选择在TDM模式输入数据端口提供了一个额外的输入路径的DSP核心配置为I2S或串行数据或7加一个20位宽的SYN -异步的并行数据采集接口通道或8通道；支持接收通道I2S音频数据，左对齐样本对，或右对齐模式信号路由单元组件之间提供所有戴配置和灵活的连接，6个串行端口，一个输入数据端口，两个精密时钟发生器，3个定时器，10个中断，六旗投入，产出6个旗，20曼谷南南区域股的I / O管脚串行外设接口的硕士或奴隶通过SPI串行启动全双工运作主从模式多主机支持开漏输出可编程波特率，时钟极性和第三期合并调制旗/ IRQ线路1合并调制旗/定时器过期线光盘的防伪特征：JTAG的访问与64位受保护的关键允许内存内存可分配给程序访问控制的限制下对敏感地区有一个代码锁相环/遥测分比率为背景的JTAG仿真功能增强的IEEE 1149.1 JTAG标准测试访问端口的软件和硬件多钳各种各样和片上仿真双电压：3.3六/输出，可在1.2 V核心136球BGA封装和144引脚LQFP封装无铅封装，也可

TDA4864 Pinout: 8- to 32-bit and 16- to 32-bit word packing options Programmable wait state options: 2 to 31 CCLK Digital audio interface includes six serial ports, two pre- cision clock generators, an input data port, three programmable timers and a signal routing unit Serial ports provide: Six dual data line serial ports that operate at up to 50 Mbits/s for a 200 MHz core on each data line each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair Left-justified sample pair and I2S support, programmable direction for up to 24 simultaneous receive or transmit channels using two I2S compatible stereo devices per serial port TDM support for telecommunications interfaces including 128 TDM channel support for telephony interfaces such as H.100/H.110 Up to 12 TDM stream support, each with 128 channels per frame Companding selection on a per channel basis in TDM mode Input data port provides an additional input path to the DSP core configurable as either eight channels of I2S or serial data or as seven channels plus a single 20-bit wide syn- chronous parallel data acquisition port Supports receive audio channel data in I2S, left-justified sample pair, or right-justified mode Signal routing unit provides configurable and flexible connections between all DAI components, six serial ports, an input data port, two precision clock generators, three timers, 10 interrupts, six flag inputs, six flag outputs, and 20 SRU I/O pins Serial peripheral interface Master or slave serial boot through SPI Full-duplex operation Master-slave mode multimaster support Open drain outputs Programmable baud rates, clock polarities, and phases 3 Muxed Flag/IRQ lines 1 Muxed Flag/Timer expired line ROM based security features: JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multi- plier/divider ratios JTAG background telemetry for enhanced emulation features IEEE 1149.1 JTAG standard test access port and on-chip emulation Dual voltage: 3.3 V I/O, 1.2 V core Available in 136-ball BGA and 144-lead LQFP packages Lead free packages are also available

TDA4864引脚说明： 8 - 32位和16 - 32位字包装选择可编程等待状态的选择：2至31个CCLK数字音频接口包括6个串行端口，两个前643时钟发生器，输入数据端口， 3可编程定时器和一个信号路由单元串行端口提供：六双串口数据线，在高达50 Mbps的操作/为200兆赫的每个数据行每个人都有一个时钟，帧同步的核心秒，和两个数据可以作为任何一个接收器或发射器对左对齐和I2S样本对支持，最多可同时接收或传送24个频道，每使用两个系列的I2S兼容立体声设备配置可编程方向线；港口的TDM通信接口，包括支持128个电话接口的TDM的渠道，如H.100/H.110支持多达12个的TDM流的支持下，每帧128个频道每个压缩扩展每通道的基础上选择在TDM模式输入数据端口提供了一个额外的输入路径的DSP核心配置为I2S或串行数据或7加一个20位宽的SYN -异步的并行数据采集接口通道或8通道；支持接收通道I2S音频数据，左对齐样本对，或右对齐模式信号路由单元组件之间提供所有戴配置和灵活的连接，6个串行端口，一个输入数据端口，两个精密时钟发生器，3个定时器，10个中断，六旗投入，产出6个旗，20曼谷南南区域股的I / O管脚串行外设接口的硕士或奴隶通过SPI串行启动全双工运作主从模式多主机支持开漏输出可编程波特率，时钟极性和第三期合并调制旗/ IRQ线路1合并调制旗/定时器过期线光盘的防伪特征：JTAG的访问与64位受保护的关键允许内存内存可分配给程序访问控制的限制下对敏感地区有一个代码锁相环/分比率背景遥测的JTAG仿真功能增强的IEEE 1149.1 JTAG标准测试访问端口软件和硬件多钳各种各样和片上仿真双电压：3.3六/输出，可在1.2 V核心136球BGA封装和144引脚LQFP封装无铅封装，也可

Chimborazo and Cotopaxi, took me by the hand.

越过琴博腊索山和科托帕克西山。

This car is in a good condition.

这辆车的状况很好。