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Thus, whenever a branch instruction is encountered the disassembly continues simultaneously at both the address following the branch instruction and the address that is the target of the branch instruction.

因此，无论何时遇到一个分支指令，就同时从两个地址继续反汇编：分支指令后面的地址和分支指令的目标地址。

The idea of Autonomous Instruction Memory is to combine Top-Level Instruction Memory and Branch Target Buffer. This kind of architecture has an character of self-generating instruction address.

自主指令记忆体的设计的想法在於结合动态分支预测器和最上层的指令记忆体而拥有自行产生指令位址的特性，因而使得CPU可以不用传送指令位址给自主指令记忆体，而达到降低CPU和自主指令记忆体之间指令位址汇流排上传递资料量的目的。

This will lead the recursive traversal algorithm to follow both the paths, the instruction immediately after the conditional jump instruction and the target of the jump instruction, potentially leading to an inconsistent state.

它将引导递归遍历算法跟随这两个路径：条件跳转指令之后紧接的那条指令和跳转指令的目标，潜在地导致一个不相容的状态。

Because SBB is going to set EAX either to zero or to 0xffffffff, we can consider the following AND instruction to be similar to a conditional assignment instruction (much like the CMOV instruction discussed later).

我们先从"与"指令说起，因为根据减法的结果，SBB将eax寄存器设为全F或全0，我们可以推出逻辑"与"的结果等价与一个条件赋值语句(类似于我们后面会讨论的CMOV指令)。

Based on a lot of experiment results, a conclusion is drawn: comparing with other factors, the performance of branch handling strategy is the key limits of processor to exploit the instruction level parallelism existed in nonscientific code, cache miss have severe effect on superscalar processor's performance when it runs scientific code. Second, in order to reduce the branch penalty and improve the performance of superscalar processor, a new branch handling strategy—a classification based hierarchical branch handling strategy, CHBHS is proposed. It first expands the traditional processor architecture to support multiple condition code, conditional execution and Mbranch instruction, as a result, compiler can reduce the number of static conditional branch when the code is generated. Then, CHBHS tries to use the best suitable mechanism to deal with different branch base on their different behavior. CHBHS can predict the target address of unconditional branch, subroutine call and conditional branch by buffering their target address in branch target buffer, a newly proposed high efficient return address stack is used to reduce the penalty of subroutine return instruction, a new Counter Register Stack is also proposed to reduce the penalty of loop-closing branch to zero, and dynamic branch predictor is incorporate with branch target buffer to predict the outcome of conditional branch.

基于上述结论，为了尽量消除转移指令对处理器开发指令级并行性能力的影响，进一步提高处理器性能，在详尽分析目前已存在的转移处理策略的特点与局限性的基础上，首次提出了一种新的转移处理策略即基于分类的层次转移处理策略CHBHS(Classification Based Hierarchical Branch Handling Strategy)，它首先通过扩展传统的体系结构，支持多条件码、条件式执行及多分支转移技术，以使编译程序在进行代码生成时可尽量少生成条件转移指令，从而减少静态条件转移指令的数目；其次，基于不同的转移指令的行为不同这一事实，提出了对不同的转移指令采用不同的机制进行处理的思想，即对无条件转移指令和函数调用指令以及条件转移指令的目标地址，采用转移目标缓冲器来预测，对于函数返回指令，采用所提出一种的高效返回地址栈来预测其目标地址，对于大多数循环控制转移指令，采用所提出的Counter Register Stack来将其所可能带来的损失减少为0，对于其他的条件转移指令采用动态预测机制来预测其方向。

To throw the disassembly off, the garbage data may be crafted so that it matches a valid instruction, thus beating a heuristic that validates the instruction after the jump instruction.

为了使反汇编陷入窘境，无用数据可能是由手工打造以便让它匹配某个有效指令；以此挫败启发式验证跳转指令之后的指令是否有效。

The controller uses the data write buffer to reduce the data access waiting time, and employs the two ways of duo channels instruction pre-fetch buffer to decrease the fetching instruction waiting time and increase the instruction pre-fetch buffer hit rate. Meanwhile, to reduce the waiting time aroused by page miss of SDRAM, a four ways of on chip stack memory is introduced. Compared with traditional controller through experiments the novel SDRAM controller gets a high reduction up to 63% in access waiting time and 64% in page miss.

该控制器采用数据写缓存方式降低了数据在存取内存时的等待时间；并引入了两组双通道预取指令缓冲器，每组双通道都用以减少取指令时的等待时间，采用两组的结构是为了增加指令预取的命中率；同时还使用了四路组关联的片上堆栈存储器来降低SDRAM的页失效频率，从而降低了因页失效而需要等待的时钟周期。

Section 10.3 of the INTEL 80386 PROGRAMMER'S REFERENCE MANUAL 1986 states : Immediately after setting the PE flag,the initialization code must flush the processor's instruction prefetch queue by executing a JMP instruction.The 80386 fetches and decodes instructions and addresses before they are used; however, after a change into protected mode, the prefetched instruction information (which pertains to real-address mode) is no longer valid.

INTEL 80386 程序员参考手册1986 中指出：在设置 PE 为1后，初始化代码必须通过一个 Jmp 指令来清空处理器取指队列，在这之前80386先完成了取指和译指和寻址，然而，在进入保护模式之后，取指指令的信息就无效了。

In accordance with the development of computer-aided instruction in China,this paper makes an analysis of the advantages and disadvantges of computer-aided instruction.Besides,the paper provides some measures to deal with the disadvantages and predicts the development trends of computer-aided instruction,such as the trends towards intellience,towards networks,and towards vir...

在总结我国计算机辅助教学发展现状的基础上，分析了计算机辅助教学的优、缺点，对于不足之处提出了应采取的措施，指出了今后计算机辅助教学的发展方向，如向智能化方向发展、向网络化的方向发展、向虚拟现实方向发展等。

This instruction should not be confused with a noop or do nothing instruction,since these generally refer to an instruction outside themselves.

这种指令不应与空操作或空指令混淆，因为取消指令通常是一种外部强制性指令。

Objective To investigate the effects of interleukin-1 β converting enzyme gene on the biologic characteristics of ovarian cancer cells.

目的 探讨白细胞介素-1 β转换酶的表达，对卵巢癌细胞生物学特性的影响。

Campylobacter: This illness is the most commonly identified cause of diarrheal illness in the world.

弯曲：这种病是最常见的原因查明腹泻病，在世界上。