查询词典 full adder

This is my ISP programming experiment in the preparation of an independent structural description of the four full-adder, through the four mapping of a full adder means four full-adder function, together with a digital display module will be full adder computing the results output to a digital display.

详细说明：这是我在ISP编程实验中独立编写的采用结构化描述的四位全加器，通过四次映射一位全加器的方式实现了四位全加器的功能，并附有数码显示模块，将全加器的运算结果输出到数码管显示。

This is a 4-bit full adder, a half-price with a make a full-adder, and then made four half adder.

详细说明：这是一个4位全加器，用一个1位半价做的一位全加，然后做成的四位半加。

In this paper, we propose a new method to implement full adder based on chaos computing. By setting different thresholds and judgment conditions, the full adder is implemented by using only one chaotic unit.

基于混沌计算的思想提出了实现全加器的新方法，通过设定不同的阀值及判断条件，使用一个混沌单元实现全加器。

The program is to achieve the n-bit full adder, first using the door with non-realization of a family - and finally realize the full n-bit adder.

该程序实现的是n位全加器，首先用与非门实现一位全家器，最后实现n位的全加器。

As an example, in the design of a 4-bit ripple carry adder, the second and fourth full adders do not use output inverters for carry generation. one inverter delay is eliminated for every two full adders in the adder chain, and four transistors are reduced. Similarly, in complex designs like the multiplier, the output inverters for generating sum and carry can be used in alternative stages, thereby improving speed and reducing area.

例如，在4位行波进位加法器中，第2级和第4级的加法器不需要用输出反向器进行进位产生，因此，加法器链上的反向器延迟每两级全加器抵消一次，因此可以减少4个晶体管，类似的，在乘法器这样的复杂设计中，用于产生"和"以及"进位"的输出反向器可以用于其它方面，因此可以改善电路的速度和减小面积。

The modification was nearly negligible in which the full adder cells are substituted by cells termed modified full adder and such design has not any additional critical paths inside the adders.

该设计改动微乎其微，通过将原有加法单元替换为一种改进的加法单元，对加法器原有关键通路无任何额外的时延影响。

We proposed 8 kinds of full adder and all of them are realized in 4 bit ripple carry adder.

在本文中，我们提出8种不同的全加器电路，分别皆使用4位元链波进位加法器将其实现。

In the max-plus environment, using vhdl language component with half adder full adder function.

详细说明：在max-plus 环境下使用vhdl语言实现用半加器组成全加器的功能。

Adder, subtractor, and multiplicer, which are included full adder, are the most common operation units in ALU.

加法、减法以及乘法等等皆是常用的运算，这些算术逻辑运算单元皆包含全加器的功能在其架构中。

Experiment include the operation of a half adder, full adder, plus / subtraction device, and the use of logic diagram VHDl descripti...

实验课的作业，包括半加器、全加器、加/减法器，使用逻辑图和VHDl描述，包括分析和报告。

The statistical analysis of this large set of mutations has led us to propose a diagnostic strategy that should help with the molecular work-up of optic neuropathies.

这一大系列基因突变的统计学分析引导我们提出一个诊断策略，可以帮助我们对视神经病变进行分子学的诊断检查。

The results show that the pipe grouting changes the mechanical parameters of surrounding rocks to achieve the security of engineering objectives by reinforcing surrounding rocks and bolcking the water.

研究表明：小导管注浆一方面改变了围岩的力学参数，另一方面利用浆液的固结特性可以实现堵水和加固围岩的工程目标，使隧道在开挖过程中的安全得到保障。