查询词典 death adder

Adder can be used to express a variety of values, such as: BCD, plus three yards, the major is based on a binary adder for computing.

加法器可以用来表示各种数值，如：BCD、加三码，主要的加法器是以二进制作运算。

In this paper, we propose a new method to implement full adder based on chaos computing. By setting different thresholds and judgment conditions, the full adder is implemented by using only one chaotic unit.

基于混沌计算的思想提出了实现全加器的新方法，通过设定不同的阀值及判断条件，使用一个混沌单元实现全加器。

In the max-plus environment, using vhdl language component with half adder full adder function.

详细说明：在max-plus 环境下使用vhdl语言实现用半加器组成全加器的功能。

The program is to achieve the n-bit full adder, first using the door with non-realization of a family - and finally realize the full n-bit adder.

该程序实现的是n位全加器，首先用与非门实现一位全家器，最后实现n位的全加器。

Adder, subtractor, and multiplicer, which are included full adder, are the most common operation units in ALU.

加法、减法以及乘法等等皆是常用的运算，这些算术逻辑运算单元皆包含全加器的功能在其架构中。

Experiment include the operation of a half adder, full adder, plus / subtraction device, and the use of logic diagram VHDl descripti...

实验课的作业，包括半加器、全加器、加/减法器，使用逻辑图和VHDl描述，包括分析和报告。

As an example, in the design of a 4-bit ripple carry adder, the second and fourth full adders do not use output inverters for carry generation. one inverter delay is eliminated for every two full adders in the adder chain, and four transistors are reduced. Similarly, in complex designs like the multiplier, the output inverters for generating sum and carry can be used in alternative stages, thereby improving speed and reducing area.

例如，在4位行波进位加法器中，第2级和第4级的加法器不需要用输出反向器进行进位产生，因此，加法器链上的反向器延迟每两级全加器抵消一次，因此可以减少4个晶体管，类似的，在乘法器这样的复杂设计中，用于产生"和"以及"进位"的输出反向器可以用于其它方面，因此可以改善电路的速度和减小面积。

The modification was nearly negligible in which the full adder cells are substituted by cells termed modified full adder and such design has not any additional critical paths inside the adders.

该设计改动微乎其微，通过将原有加法单元替换为一种改进的加法单元，对加法器原有关键通路无任何额外的时延影响。

Experiments on multiplier tree and adder tree expressions exhibit running time reduction of 83% to 99%, and 40% to 80% respectively.4. Arithmetic unit check with half adder graph technique: Binary Moment Diagram technique has been used in multiplier equivalence checking.

比如针对加法和乘法连续运算的表达式，算法从实现电路中提取变量顺序和结合顺序并加以利用，实验表明，在验证乘法连续运算的表达式时减少了83%～99%的时间，加法连续运算表达式的验证时间也可减少40%～89%。4。

The algorithm combines the recognition technique of different coding methods in multiplier, the extraction technique of half adder graph in addition circuit, and the recognition technique of half adder tree structure of partial product addition circuit. With the extracted information, the register transfer level synthesis engine can generate a gate netlist that is logically correct and structurally similar to the implementation.

该算法结合了乘法器的编码方式识别技术、加法电路的半加树提取技术和部分积加法电路的架构识别技术来提取乘法电路的实现结构，以此生成与实现电路结构相似且逻辑正确的网表。

There had been a moment during the breakfast meeting, though, after the backslapping and the small talk and when all of us were seated, with Vice President Cheney eating his eggs Benedict impassively and Karl Rove at the far end of the table discreetly checking his BlackBerry, that I witnessed a different side of the man.

那次早餐会期间，在表示过关心和寒暄以后，我们所有人坐了下来，我注意观察了一下，副总统切尼面无表情地吃着班尼迪克蛋（Eggs benedict，源自美国，以英式松饼、火腿、水煮蛋以及荷兰酱组合而成），卡尔。罗夫在餐桌的远端谨慎地经常查看他的黑莓手机，我目睹了他所不为人知的一面。

Talk Undelete failed; someone else may have undeleted the page first.

Talk 无法删除选定的页面或图像（它可能已经被其他人删除了）。