查询词典 address bus

But there are also Alphas where the physical address and the bus address are the same.

然而，在某些Alphas机器上面，物理地址和总线地址是相同的

Sending LE_ARP packets for the broadcast address returns the ATM address of the BUS.

为了广播地址请求而发送的LE_ARP包将返回总线的ATM地址。

Extended Industry Standard Architecture expansion bus, based on the IBM PC AT bus, but extended to 32 bits of address and data.

以 IBM PC AT 总线为基础实现的扩展工业标准结构总线，但是地址和数据均扩展到32位。

The circuit comprises a comparison circuit, a negation gate and a first coincidence gate, wherein the comparison circuit is used to output read screen signals of a storage unit corresponding with bus signals of a second port address, the negation gate is used to inverse the read screen signals of the storage unit which are corresponding with the bus signals of the second port address, one input end of the first coincidence gate receives the read screen signals of the storage unit which are corresponding with the bus signals of the second port address after being inversed, the other input end of the first coincidence gate receives the read enable signals of a second port, and the output end of the first coincidence gate is connected with the read enable end of the second port.

所述电路包括：比较电路，用于输出第二端口地址总线信号对应的存储单元读屏蔽信号；非门，用于对第二端口地址总线信号对应的存储单元读屏蔽信号进行非运算；第一与门，第一与门的一路输入端接收非运算后的第二端口地址总线信号对应的存储单元读屏蔽信号，第一与门的另一路输入端接收第二端口的读使能信号，第一与门的输出端连接第二端口的读使能端。

C Supports both Firmware Hub and LPC Memory Read and Write Cycles Auto-detection of FWH and LPC Memory Cycles C Can Be Used as FWH for Intel 8xx, E7xxx, and E8xxx Series Chipsets C Can Be Used as LPC Flash for Non-Intel Chipsets Flexible, Optimized Sectoring for BIOS Applications C 16-Kbyte Top Boot Sector, Two 8-Kbyte Sectors, One 32-Kbyte Sector, Three 64-Kbyte Sectors C Or Memory Array Can Be Divided Into Four Uniform 64-Kbyte Sectors for Erasing Two Configurable Interfaces C FWH/LPC Interface for In-System Operation C Address/Address Multiplexed Interface for Programming during Manufacturing FWH/LPC Interface C Operates with the 33 MHz PCI Bus Clock C 5-signal Communication Interface Supporting Byte Reads and Writes C Two Hardware Write Protect Pins: TBL for Top Boot Sector and WP for All Other Sectors C Five General-purpose Input Pins for System Design Flexibility C Identification Pins for Multiple Device Selection C Sector Locking Registers for Individual Sector Read and Write Protection A/A Mux Interface C 11-pin Multiplexed Address and 8-pin Data Interface C Facilitates Fast In-System or Out-of-System Programming Single Voltage Operation C 3.0V to 3.6V Supply Voltage for Read and Write Operations Industry-Standard Package Options C 32-lead PLCC C 40-lead TSOP

0第0页，本页显示记录0-0，共0条记录分0页显示C支持两种固件中心和LPC内存读取和写入周期自动的FWH和LPC的记忆圈C检测可以用于英特尔8xx系列，E7xxx，E8xxx系列芯片组和C可以用作FWH与至于非英特尔芯片组的BIOS应用柔性优化扇区开放16字节热门引导扇区，两个8 - Kbyte的，一个32字节部门，3个64 - Kbyte的C或存储阵列，线性预测编码闪光可分为四个统一为两个可配置的接口擦除的FWH / LPC接口为64 - Kbyte的行业，系统运行C地址/地址多路复用在制造过程中用于编程接口的FWH /线性预测编码界面C与33 MHz的PCI总线时钟 5信号通信接口进行操作，支持字节读取和写入引导扇区的顶部和WP C两硬件写保护引脚：任务型为所有其他部门 5个通用输入的系统设计的灵活性识别的多种设备选型部门登记销锁定为个别部门读取和写保护的A /阿复用界面C 11引脚复用引脚地址和8引脚的数据界面C促进快速系统内或外的系统编程的单电压3.0V至3.6V的操作供应的读取和写入操作业界标准的封装选项电压 32 -引脚PLCC 40引脚的TSOP

It is proved that the new arithmetic is the best way to minish the transition probability of the signal of program address bus.

实现了程序地址总线的编解码电路，并应用于16位定点1KSPIP核设计，使程序地址总线功耗降低了76.4％。

This is not possible with a Von Neumann single-address bus architecture.

这是不可能的了冯诺伊曼单地址总线架构。

This method reorders the ten least significant bits of offset address according to the value of offset address, and the optimal sorting pattern is transmitted through the high bits of bus without the need for redundant bus lines.

该编码方法根据偏移地址的值域对地址总线的低位进行优化重排，通过高位地址总线传送排序矢量至存储器的地址接收端，相对于传统的地址总线编码方法，具有更低的总线跳变率。

Big-Endian ConfigurationA signed byte load expects data on data bus inputs 31 through to 24 if the supplied address is on aword boundary, on data bus inputs 23 through to 16 if it is a word address plus one byte, and so on.

大尾段配置阿签署字节负载预计在31日的数据总线输入数据，如果通过向24所提供的地址上的字的边界，数据总线投入23日至16如果它是一个字地址加上一个字节，依此类推。

Pinout: C High-performance 32-bit RISC Architecture C High-density 16-bit Instruction Set C Leader in MIPS/Watt C Little-endian C Embedded ICE (In-circuit Emulation) 8-, 16- and 32-bit Read and Write Support 256K Bytes of On-chip SRAM C 32-bit Data Bus C Single-clock Cycle Access Fully Programmable External Bus Interface C Maximum External Address Space of 64M Bytes C Up to Eight Chip Selects C Software Programmable 8/16-bit External Data Bus Eight-level Priority, Individually Maskable, Vectored Interrupt Controller C Four External Interrupts, including a High-priority, Low-latency Interrupt Request 32 Programmable I/O Lines Three-channel 16-bit Timer/Counter C Three External Clock Inputs C Two Multi-purpose I/O Pins per Channel Two USARTs C Two Dedicated Peripheral Data Controller Channels per USART Programmable Watchdog Timer Advanced Power-saving Features C CPU and Peripheral Can be Deactivated Individually Fully Static Operation: C 0 Hz to 75 MHz Internal Frequency Range at VDDCORE = 1.8V, 85C 2.7V to 3.6V I/O Operating Range 1.65V to 1.95V Core Operating Range -40C to +85C Temperature Range Available in 100-lead TQFP Package

M5L8253P-5引脚说明： C型高性能32位RISC架构C高密度以MIPS /瓦C小端C十六位指令集C领袖嵌入式冰8 - 16 -位和32位的读写支持256K的片上SRAM的 32位数据总线C单时钟周期存取字节完全可编程的外部总线接口C最大的外部地址空间的64M字节多达8个C芯片选择C软件可编程8位外部数据总线8级优先级，独立可屏蔽，向量中断控制器C四外部中断，其中包括一个高优先级，低延迟中断要求32个可编程I / O口线三通道16位定时器/计数器C三个外部时钟输入C两多用途I / O引脚每通道2个通用同步C两专用外设数据控制器通道每个USART可编程看门狗定时器先进的节能特性 CPU和外设可停用独立全静态工作中：C 0 Hz至75 MHz的频率范围内的VDDCORE = 1.8，85℃2.7V到3.6VI / O的操作1.65V到1.95V范围核心工作电压范围在- 40C至+85 C温度范围内使用的100引脚TQFP封装

But in the course of internationalization, they meet with misunderstanding and puzzlement.

许多企业已经意识到了这一点，但在国际化的进程中，仍存在一些误区与困惑。

Inorder toaccomplish this goal as quickly as possible, we'll beteamingup with anexperienced group of modelers, skinners, and animatorswhosenames willbe announced in the coming weeks.

为了尽快实现这个目标，我们在未来数周内将公布与一些有经验的模型、皮肤、动画制作小组合作。