输入线

词组短语

incoming line

与输入线相关的网络例句 [注：此内容来源于网络，仅供参考]

The sensor unit includes provisions to collect auxiliary data such as sensor temperature and/or the state of two digital input and two digital output lines.

传感器单元内含装置收集辅助数据，例如传感器温度和/或两路数字输出和两路数字输入线的状态。

Transmit Softclipping Time Constant Receiving Input Sidetone Network Input Line Current Regulation Stop Value Microphone Input Microphone Input Transmit Gain Adjustment Transmit and Receive Part Power Supply Ground Line Current Source Power Supply Voltage Stabilizer Positive Line Unregulated Microcontroller Power Supply Receive Gain Adjustment Negative Earphone Output Positive Earphone Output Ringer Buzzer Output Ring Power Supply Reset Power On Ring Indicator Oscillator Input Mask, Ring Melody Input Data Input Data Clock Input Microcontroller Stabilized Power Supply Reference Voltage (VCC/2) DTMF Filter

1第1页，本页显示记录1-8，共8条记录分1页显示发送Softclipping时间常数接收输入侧音网络输入线电流调节停止价值麦克风输入麦克风输入发射增益调整发送和接收部分电源地线电流源电源稳压器的正电源线无管制的单片机接收增益调整负耳机输出耳机输出正林格蜂鸣器输出电源供应环环指标振荡器输入掩码电复位，环旋律输入数据输入数据时钟输入单片机的稳定电源参考电压（Vcc / 2）双音多频滤波器

The results showed that input linearly polarized and circularly polarized light will not produce nonlinear polarization rotation, and only the elliptically polarized light will produce nonlinear polarization rotation.

结果表明，输入线偏振光与圆偏振光都不会产生非线性旋转，只有椭圆偏振光才有非线性旋转。

But disconnect the load and the output correctly, in the time, I fail to understand why it suddenly occurred to power does not output voltage may also be due to eircuit the power protection, since switching power supply does not have the problem, according to the circuit diagram check switching power supply external power supply module one by one, if the hinge-counter, discovered its signal line wrap wire close to counter one end of the triadha into the signal lines, causing a short circuit input line.

可是断开负载，其输出正常，在百思不得其解之时，笔者突然想到电源不能正常输出电压也有可能是由于负载短路使电源保护造成的，既然开关电源本身没有问题，按照电路图检查开关电源外围的供电模块逐一排查，当检查到折页计数器时，无意中发现其信号线外缠绕的钢丝线接近计数器的一端扎进了信号线中，造成输入线短路。

A device that has a number of input lines of which not more than one at a time may carry a signal and a number of output lines of which any number may carry signals, there being a one to one correspondence between the combinations of the output signals and the input signals.

具有多条输入线和多条输出线的一种设备，输入线中一次最多只有一条线载有信号，但输出线中可有多个线载有信号。输出信号和输入信号的组合之间存在一一对应的关系。

Inputs and Outputs Front Panel: Phones: Standard headphone output jack (gold-plated) Video 4: Gold-plated stereo RCA jacks, gold-plated RCA composite video jack and S-video jack Digital Optical 3 Input: Standard Toslink digital input with a plastic protective plug Digital Coax 3 Input: Standard gold-plated coaxial digital jack Back Panel: AM Loop Antenna Input: Two thumb screw connections FM 75-ohm Antenna input: Threaded "F" type connector Tape Input/Output: Stereo RCA jacks Video 3 Input: Stereo RCA jacks, RCA composite video jack and S-video jack Video 2 Input/Output: Stereo RCA jacks, RCA composite video jacks and S-video jacks Video 1 Input/Output: Stereo RCA jacks, RCA composite video jacks and S-video jacks DVD Input: Stereo RCA jacks, RCA composite video jack, and S-video jack CD Input: Stereo RCA jacks Monitor Output: RCA composite video jack and S-video jack Subwoofer Preamp Output: 1 RCA jack Digital Optical 1 Input: Standard Toslink digital input with a plastic protective plug Digital Optical 2 Input: Standard Toslink digital input with a plastic protective plug Digital Coax 1 Input: Standard coaxial digital jack Digital Coax 2 Input: Standard coaxial digital jack Digital Optical Output: Standard Toslink digital output with a plastic protective plug Digital Coax Output: Standard coaxial digital jack Remote Control In/Out Jacks: One mini-jack input and one mini-jack output Speaker Outputs: Binding post outputs for front left, front right, surround left, surround right, and center speakers (posts are not 5-way binding posts, because each post has a plastic collar that prevents used with spade lugs and the posts are too far apart to use dual banana plugs) AC Outlets: One unswitched AC outlet and one switched AC outlet

投入和产出接待小组：电话：标准耳机输出插孔视频4 ：镀金立体声RCA插孔，镀金的RCA复合视频插孔和S - Video插孔数字光学3输入：标准Toslink数字输入与一个塑料保护插头数字同轴3输入：标准镀金同轴数字接口背板：上午环形天线输入：两个拇指螺丝连接调频75欧姆天线输入：线程的& F &型连接器，磁带输入/输出：立体声RCA插孔视频3输入：立体声RCA插孔，插孔的RCA复合视频和S - Video插孔视频2输入/输出：立体声RCA插孔，莲花复合视频插孔和S - Video插孔视频1输入/输出：立体声RCA插孔，插孔的RCA复合视频和S端子接口的DVD输入：立体声RCA插孔，插孔的RCA复合视频和S -视频CD输入端插孔：立体声RCA插孔监视器输出：复合视频的RCA插孔和S - Video插孔低音前置输出： 1的RCA插孔数字光1输入：标准Toslink数字输入与一个塑料保护插头数字光2输入：标准Toslink数字输入与一个塑料保护插头数字同轴输入1 ：标准同轴数字接口数字同轴2输入：同轴数字接口标准数字光输出：标准Toslink数字输出塑料防护插件数字同轴输出：标准同轴数字接口远程控制在/输出插孔：一个迷你插孔输入和1个小型插孔输出扬声器输出：结合后产出的左前方，右前方，左环绕，右环绕和中心发言（职位不是5个具有约束力的方式，因为每个职位有一个塑料环，可以防止使用铁锹派和职位过于遥远使用双香蕉插头）交流插座：一个unswitched AC插座和一个开关AC电源插座

First connect the black ground lead, then connect the orange/white striped, yellow and red power input leads.

首先连接黑色地线，然后连接橙色／白色条纹线、黄色和红色电源输入线。

MAX1999EEI Pinout: 8- to 32-bit and 16- to 32-bit word packing options Programmable wait state options: 2 to 31 CCLK Digital audio interface includes six serial ports, two pre- cision clock generators, an input data port, three programmable timers and a signal routing unit Serial ports provide: Six dual data line serial ports that operate at up to 50 Mbits/s for a 200 MHz core on each data line each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair Left-justified sample pair and I2S support, programmable direction for up to 24 simultaneous receive or transmit channels using two I2S compatible stereo devices per serial port TDM support for telecommunications interfaces including 128 TDM channel support for telephony interfaces such as H.100/H.110 Up to 12 TDM stream support, each with 128 channels per frame Companding selection on a per channel basis in TDM mode Input data port provides an additional input path to the DSP core configurable as either eight channels of I2S or serial data or as seven channels plus a single 20-bit wide syn- chronous parallel data acquisition port Supports receive audio channel data in I2S, left-justified sample pair, or right-justified mode Signal routing unit provides configurable and flexible connections between all DAI components, six serial ports, an input data port, two precision clock generators, three timers, 10 interrupts, six flag inputs, six flag outputs, and 20 SRU I/O pins Serial peripheral interface Master or slave serial boot through SPI Full-duplex operation Master-slave mode multimaster support Open drain outputs Programmable baud rates, clock polarities, and phases 3 Muxed Flag/IRQ lines 1 Muxed Flag/Timer expired line ROM based security features: JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multi- plier/divider ratios JTAG background telemetry for enhanced emulation features IEEE 1149.1 JTAG standard test access port and on-chip emulation Dual voltage: 3.3 V I/O, 1.2 V core Available in 136-ball BGA and 144-lead LQFP packages Lead free packages are also available

MAX1999EEI引脚说明： 8 - 32位和16 - 32位字包装选择可编程等待状态的选择：2至31个CCLK数字音频接口包括6个串行端口，两个前643时钟发生器，输入数据端口， 3可编程定时器和一个信号路由单元串行端口提供：六双串口数据线，在高达50 Mbps的操作/为200兆赫的每个数据行每个人都有一个时钟，帧同步的核心秒，和两个数据可以作为任何一个接收器或发射器对左对齐和I2S配对样本的支持下，最多可同时接收或传送24个频道，每使用两个系列的I2S兼容立体声设备配置可编程方向线；港口的TDM通信接口，包括支持128个电话接口的TDM的渠道，如H.100/H.110支持多达12个的TDM流的支持下，每帧128个频道每个压缩扩展每通道的基础上选择在TDM模式输入数据端口提供了一个额外的输入路径的DSP核心配置为I2S或串行数据或7加一个20位宽的SYN -异步的并行数据采集接口通道或8通道；支持接收通道I2S音频数据，左对齐样本对，或右对齐模式信号路由单元组件之间提供所有戴配置和灵活的连接，6个串行端口，一个输入数据端口，两个精密时钟发生器，3个定时器，10个中断，六旗投入，产出6个旗，20曼谷南南区域股的I / O管脚串行外设接口的硕士或奴隶通过SPI串行启动全双工运作主从模式多主机支持开漏输出可编程波特率，时钟极性和第三期合并调制旗/ IRQ线路1合并调制旗/定时器过期线光盘的防伪特征：JTAG的访问与64位受保护的关键允许内存内存可分配给程序访问控制的限制下对敏感地区有一个代码锁相环/遥测分比率为背景的JTAG仿真功能增强的IEEE 1149.1 JTAG标准测试访问端口的软件和硬件多钳各种各样和片上仿真双电压：3.3六/输出，可在1.2 V核心136球BGA封装和144引脚LQFP封装无铅封装，也可

TDA4864 Pinout: 8- to 32-bit and 16- to 32-bit word packing options Programmable wait state options: 2 to 31 CCLK Digital audio interface includes six serial ports, two pre- cision clock generators, an input data port, three programmable timers and a signal routing unit Serial ports provide: Six dual data line serial ports that operate at up to 50 Mbits/s for a 200 MHz core on each data line each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair Left-justified sample pair and I2S support, programmable direction for up to 24 simultaneous receive or transmit channels using two I2S compatible stereo devices per serial port TDM support for telecommunications interfaces including 128 TDM channel support for telephony interfaces such as H.100/H.110 Up to 12 TDM stream support, each with 128 channels per frame Companding selection on a per channel basis in TDM mode Input data port provides an additional input path to the DSP core configurable as either eight channels of I2S or serial data or as seven channels plus a single 20-bit wide syn- chronous parallel data acquisition port Supports receive audio channel data in I2S, left-justified sample pair, or right-justified mode Signal routing unit provides configurable and flexible connections between all DAI components, six serial ports, an input data port, two precision clock generators, three timers, 10 interrupts, six flag inputs, six flag outputs, and 20 SRU I/O pins Serial peripheral interface Master or slave serial boot through SPI Full-duplex operation Master-slave mode multimaster support Open drain outputs Programmable baud rates, clock polarities, and phases 3 Muxed Flag/IRQ lines 1 Muxed Flag/Timer expired line ROM based security features: JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multi- plier/divider ratios JTAG background telemetry for enhanced emulation features IEEE 1149.1 JTAG standard test access port and on-chip emulation Dual voltage: 3.3 V I/O, 1.2 V core Available in 136-ball BGA and 144-lead LQFP packages Lead free packages are also available

TDA4864引脚说明： 8 - 32位和16 - 32位字包装选择可编程等待状态的选择：2至31个CCLK数字音频接口包括6个串行端口，两个前643时钟发生器，输入数据端口， 3可编程定时器和一个信号路由单元串行端口提供：六双串口数据线，在高达50 Mbps的操作/为200兆赫的每个数据行每个人都有一个时钟，帧同步的核心秒，和两个数据可以作为任何一个接收器或发射器对左对齐和I2S样本对支持，最多可同时接收或传送24个频道，每使用两个系列的I2S兼容立体声设备配置可编程方向线；港口的TDM通信接口，包括支持128个电话接口的TDM的渠道，如H.100/H.110支持多达12个的TDM流的支持下，每帧128个频道每个压缩扩展每通道的基础上选择在TDM模式输入数据端口提供了一个额外的输入路径的DSP核心配置为I2S或串行数据或7加一个20位宽的SYN -异步的并行数据采集接口通道或8通道；支持接收通道I2S音频数据，左对齐样本对，或右对齐模式信号路由单元组件之间提供所有戴配置和灵活的连接，6个串行端口，一个输入数据端口，两个精密时钟发生器，3个定时器，10个中断，六旗投入，产出6个旗，20曼谷南南区域股的I / O管脚串行外设接口的硕士或奴隶通过SPI串行启动全双工运作主从模式多主机支持开漏输出可编程波特率，时钟极性和第三期合并调制旗/ IRQ线路1合并调制旗/定时器过期线光盘的防伪特征：JTAG的访问与64位受保护的关键允许内存内存可分配给程序访问控制的限制下对敏感地区有一个代码锁相环/分比率背景遥测的JTAG仿真功能增强的IEEE 1149.1 JTAG标准测试访问端口软件和硬件多钳各种各样和片上仿真双电压：3.3六/输出，可在1.2 V核心136球BGA封装和144引脚LQFP封装无铅封装，也可

The first generation: there is only one signal input wire, which can be connected to all Korean cars and some of American cars.

第一代是：世界上只有一个信号输入线、可连接所有的韩国车和美国有些车。

与输入线相关的网络解释 [注：此内容来源于网络，仅供参考]

AIN：模拟输入

SDA 线上从高到低的跳变当时钟(SCL)为高电平时,SDA 线上从低到高的跳变节时不产生应答(NAK)来向从器件发出数据结束信件控制总线,由其产生串行时钟(SCL)控制总线的访MCP3021 具有一个单端模拟输入(AIN)引脚.

multithread application program：多线应用程序

多线 multithread | 多线应用程序 multithread application program | 多线输入 multithread input

Data-in：数据输入

每个器件具有芯片选择(CS) 、输入-输出时钟(I/O CLK) 、数据输入(DATA IN)以及数据输出(DATA OUT) ,能提供主微处理器的直接4线同步串行外设接口(SPITM,QSPITM)端口.

feed in：输入

这将由输入(feed in)和馈线来完成. 为了把最大的信号从天线转移到馈线上,馈线的阻抗必须和天线的输入点阻抗(feed point impedance) 匹配. 大部分的半波天线,这数值是在50和75欧姆之间. 因此,50或75欧姆同轴馈线可被使用.

input：输入电脑

声音从电脑类比输出(Output)的地方,连接:声音类比输入电脑(Input)的地方,连接所有电脑声音的输入、录制的音量,都可以在此控制,并可以选择录制的音源,如选择麦克风、光碟机或是输入线(Line In)中的音源.

lead-in clamp：引入线夹,输入接线柱

lead-in cable 引込ケーブル | lead-in clamp 引入线夹,输入接线柱 | lead-in conductor 引入导线

MUTE：哑音(键)

C:大两芯输入线是否插在了插入口(INSERT)中 D:输入编组是否打开 E:音源输入单路的哑音键(MUTE)是否位置正确 6 . 声音发噼 A:拾取声音超过话筒拾音动态 B:音源录制时不好 C:音源在调音台输入的(GAIN*TRIM)增益调节过大 D:所有设备与功放线路的电平设置是否正确 7 .

cycloidal gear：摆线齿轮

图 13:摆线齿轮(Cycloidal Gear)为例之外形图 14:特殊凸形圆弧齿轮(Novikov gear)之输入画面图 15:特殊凸形圆弧齿轮(Novikov gear)之外形图 16:特殊凹形圆弧齿轮(Novikov gear)之输入画面图 17:特殊凹形圆弧齿轮(Novikov gear)之外形之工程维修人员甚至可直接透过数据机(Modem)进行顾客磨齿机之维修,

power leadin：电源输入线

电源设备 power equipment | 电源输入线 power leadin | 电源系统 power system

TCK：测试时钟输入

设计人员应该使用相同的指导方针来设置JTAG测试时钟输入(TCK)信号作为系统时钟. 此外,把一个器件的测试数据输出和另一个器件的测试数据输入之间的JTAG扫描链线迹长度减至最短也是相当重要的. 要利用嵌入式高速FPGA进行成功的设计,