存储器寄存器

词组短语

memory register

与存储器寄存器相关的网络例句 [注：此内容来源于网络，仅供参考]

It allows one base register to be used to access a number of memory locations which are in the same area of memory.

采用这种模式可以使用一个基址寄存器来访问位于同一区域的多个存储器单元。

The train positioning technology based on absolute position encoding is proposed. The absolute positions of the rail track are encoded with the m sequence. The biconditional markers placed on the rail track are detected sequentially by the train-borne reader. The exclusive position code consists of the binary information in the shift register. The absolute train positioning information can be extracted by decoding this position code.

利用m序列（最大周期线性反馈移位寄存器序列）对轨道线路上的绝对位置进行编码，当列车在线路上运行时，通过车载阅读器顺序检测设置在轨道线路上的二值标记，在不同位置上读到的标记在移位存储器中构成唯一的位置编码，以此位置编码值作为地址与车载阅读器所处位置的坐标信息相对应，就可以实现列车的绝对定位。

Then, on the basis of the functional verification, the system architectures of the radio frequency analog front end and the control logic circuit for the passive UHF RFID transponder are studied and designed with low-power design techniques. The RF AFE circuit includes rectifier, matching network, backscatter, regulator, AM demodulator, voltage reference, local oscillator and power on reset circuit, and so on. The control logic circuit contains clock synchronization module, decoding module, coding module, cyclic redundancy checksum module, power management unit, control unit, shift register and memory.

然后，在功能验证的基础上，重点研究了无源超高频射频识别标签芯片射频模拟前端电路和控制逻辑电路的系统架构，并采用低功耗设计技术对其进行了设计，射频模拟前端电路设计包括了整流器、匹配网络、反向散射电路、稳压器、AM解调器、电压参考源、本地振荡器以及上电复位电路等，控制逻辑电路设计包括了时钟同步模块、解码模块、编码模块、CRC校验模块、功率管理单元、控制单元、移位寄存器和存储器等。

A Read Data from Memory instruction loads the address of the first byte or word to be read in an internal address register.

从存储器指令加载的第一个字节或字地址读取数据被读在内部地址寄存器。

TL084MJ Pinout: 3.3V Operation with 5V Tolerant Buffers ACPI 1.1, PC99/PC2001 Compliant LPC Interface with Clock Run Support Serial IRQ Interface Compatible with Serialized IRQ Support for PCI Systems 15 Direct IRQs Four 8-Bit DMA Channels ACPI SCI Interface nSMI Shadowed write only registers Internal 64K Flash ROM Programmed From Direct Parallel Interface, 8051, or LPC Host 2k-Byte Lockable Boot Block Can be Programmed Without 8051 Intervention Three Power Planes Low Standby Current in Sleep Mode Intelligent Auto Power Management for Super I/O ACPI Embedded Controller Interface Configuration Register Set Compatible with ISA Plug-and-Play Standard (Version 1.0a) High-Performance Embedded 8051 Keyboard and System Controller Provides System Power Management System Watch Dog Timer 8042 Style Host Interface Supports Interrupt and Polling Access 256 Bytes Data RAM On-Chip Memory-Mapped Control Registers Access to RTC and CMOS Registers Up to 16x8 Keyboard Scan Matrix Two 16 Bit Timer/Counters Integrated Full-Duplex Serial Port Interface Eleven 8051 Interrupt Sources Thirty-Two 8-Bit, Host/8051 Mailbox Registers Thirty-six Maskable Hardware Wake-Up Events Fast GATEA20

TL084MJ引脚说明： 3.3V工作电压为5V容错缓冲器的ACPI 1.1，PC99/PC2001符合LPC接口与时钟运行支持-兼容串行接口与串行的IRQ IRQ的支持PCI系统- 15直接的IRQ - 4个8位DMA通道- ACPI的SCI接口- nSMI -阴影只写寄存器内部的64K的Flash ROM -直接从程序并行接口，8051，还是LPC主机-的2K字节可锁定引导块-可在不干预程序8051三力飞机-低待机电流在休眠模式-智能型自动电源管理的超级I / O的ACPI嵌入式控制器接口配置寄存器设置兼容的ISA拆开的播放标准（版本1.0a）高性能嵌入式8051键盘和系统控制器-提供系统电源管理-系统监视狗定时器- 8042型主机接口-支持中断和轮询访问- 256字节数据RAM -片上存储器映射控制寄存器-获取实时时钟和CMOS寄存器-最多16x8矩阵键盘扫描- 2个16位定时器/计数器-综合全双工串行接口- 11个中断源8051 - 32个8位，Host/8051邮箱寄存器- 36个可屏蔽硬件唤醒事件-快速GATEA20

It uses the instruction character to determine if the memorizer or the register is accessed.

利用指令的性质来确定是对内存数据存储器访问还是对内存映射寄存器访问。

Figure 7., shows the Protection Register Memory Map.

图7。，显示了保护寄存器的存储器映射。

Contents of a memory location or register within a particular peripheral, ints on the data bus.

设中的存储器地址或寄存器中的内容时，处理器设置地址总线并在数据总线上接收

The rest of this article time control system is composed of MCS-51 Microcontroller AT89S51 do the main control unit, the external circuit with a 12MHZ crystal oscillator, 74LS164 registers, reset circuit, three buttons, LED digital tube to do quadruple the time of the device shows no the needs of extended memory, can achieve its functions.

本文所研究的作息时间控制系统是由MCS-51系列单片机AT89S51做主控部件，外围电路用12MHZ晶体震荡器、74LS164寄存器、复位电路、三个按键、四联LED数码管做显示时间的器件，不需要外扩展存储器，就能实现其功能。

The data location includes memory data memorizer and memory map register, which share uniform data and address buses, at the same time occupy independent physical spaces, respectively, both physical and logic addresses separated and independently addressed, respectively, and can multiplex the same logic address.

内存数据存储器和内存映射寄存器共享统一的数据总线和数据地址总线。同时，内存数据存储器和内存映射寄存器各自占有独立的物理空间，物理地址和逻辑地址均分开，各自独立编址，内存数据存储器和内存映射寄存器对同一逻辑地址可以复用。

与存储器寄存器相关的网络解释 [注：此内容来源于网络，仅供参考]

memory address register：存储地址寄存器

memorizer panel 存储器控制面板 | memory address register 存储地址寄存器 | memory address space 存储地址空间

memory address register：存储器地址寄存器

存储管|storage tube | 存储器地址寄存器|memory address register | 存储示波器|storage oscilloscope

addressable register：可寻址寄存器可编址寄存器

addressable point 可寻址点 | addressable register 可寻址寄存器可编址寄存器 | addressed memory 编址存储器

addressable register：可寻址寄存器

addressable memory 可访问存储器 | addressable register 可寻址寄存器 | addressable 可访问的

base register：基地址寄存器

累加器可用于乘、除、输入/输出等操作,它们的使用频率很高;寄存器BX称为基地址寄存器(Base Register). 它可作为存储器指针来使用; 寄存器CX称为计数寄存器(Count Register). 在循环和字符串操作时,要用它来控制循环次数;在位操作中,

Data Buffer Register：数据缓冲寄存器

data buffer local storage 数据缓冲局部存储器 DBLS | data buffer register 数据缓冲寄存器 | data buffer unit 数据缓冲器 DBU

global memory：全局存储器

每一个线程拥有自己的私有存储器寄存器和局部存储器;每一个线程块拥有一块共享存储器(Shared memory);最后,grid中所有的线程都可以访问同一块全局存储器(Global memory).

GREG Global Memory Allocation Register：全局存储器配置寄存器

DP Data Memory Page Pointer 数据存储器页面指针 | GREG Global Memory Allocation Register 全局存储器配置寄存器 | IMR Interrupt Mask Register 中断屏蔽寄存器

MOR MemoryOutputRegister：存储器输出寄存器

MO MemoryOutput 存储器输出 | MOR MemoryOutputRegister 存储器输出寄存器 | MP MemoryPointer 存储器指示器

scratch pad register：暂存寄存器

scratch pad memory 暂时存储器便笺式存储器 | scratch pad register 暂存寄存器 | scratch tape 暂存带