串行连接

词组短语

series connection

与串行连接相关的网络例句 [注：此内容来源于网络，仅供参考]

Serial ATA is the evolution of the ATA interface from a parallel bus to serial connection architecture.

串行ATA是ATA接口的演变，从ATA的并行总线演变成为串行连接的结构。

A serial connection transfers only one piece of data at a time while a parallel connection transfer blocks of information at the same time.

串行连接传输的一次只能有一个数据片，同时并行连接的信息传输块在同一时间

Pinout for an adapter to connect a 9-pin female serial connector to a 25-pin male serial cable.

引脚为一个适配器连接9针女串行连接到一个25针男串行电缆。

The design of the modern electronic device, except for must has multiple functions, but it also trend to achieve slightness, thinness, shortness and smallness in outer appearance. In order to seek such a trend, the components disposed in the electronic device must be reduced in volume correspondingly, and the connectors used therein also must be reduced in volume without exception. For example, the USB connector has developed a mini USB connector, and the digital video signal transmission interface evolves from a digital video interface to a high definition multi-media interface having a smaller volume and a faster transmission speed.

现代电子产品的设计除了要功能多样外，在外观上的趋势是追求轻、薄、短、小，为了追求这样的趋势，电子产品内的各个零件也必须跟着将体积缩小，其所使用的电连接器当然也不例外，如通用串行连接埠推出迷你版的通用串行连接端口，而数字影音讯号的传输接口也由数字视觉接口推演到体积较小，传输速度更快的高速高解析多媒体接口。

The crystal oscillator provides frequency stable accurate 32768Hz the signal. After frequency divider frequency division to 1Hz stable accurate function signal,Does for the counter pulse signal. Six counter serial connections,Uses the decimal base and the senary counting separately (when ten for ternary notation counting). Comes out through 7448 decoders and the monitor appearances,The counting cycle is 24 hours.

晶振提供一个频率稳定准确的32768Hz的信号，经过分频器分频的到1Hz稳定准确的函数信号，做为计数器的脉冲信号，六个计数器串行连接，分别采用十进制和六进制计数，通过7448译码器和显示器显现出来，计数周期为24小时。

In addition, the serial link includes an OAM (Opera- tions and Maintenance) channel that does not detract from link performance.

此外，包括一个串行连接的OAM渠道并不影响链路性能。

Let us consider a serial concatenated system as shown in Fig.

让我们来看看Fig.1中所示的串行连接系统。

The apparatus further includes a quad-symbol mapper which quad-maps the systematic symbol streams to one symbol stream, a channel interleaver which independently interleaves the quad-mapped systematic symbol stream and the parity symbol streams, quad-demaps the quad-mapped systematic symbol stream, interlaces symbols in parity symbol streams, and serial-concatenates the quad-demapped systematic symbol stream to the interlaced parity symbol streams.

该设备还包括：四码元映射器，其将系统码元流四映射到一个码元流；信道交织器，其独立地交织四映射的系统码元流和奇偶码元流，对四映射的系统码元流进行四逆映射，交错奇偶码元流中的码元，并且将四逆映射的系统码元流串行连接为交错的奇偶码元流。

MAX1999EEI Pinout: 8- to 32-bit and 16- to 32-bit word packing options Programmable wait state options: 2 to 31 CCLK Digital audio interface includes six serial ports, two pre- cision clock generators, an input data port, three programmable timers and a signal routing unit Serial ports provide: Six dual data line serial ports that operate at up to 50 Mbits/s for a 200 MHz core on each data line each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair Left-justified sample pair and I2S support, programmable direction for up to 24 simultaneous receive or transmit channels using two I2S compatible stereo devices per serial port TDM support for telecommunications interfaces including 128 TDM channel support for telephony interfaces such as H.100/H.110 Up to 12 TDM stream support, each with 128 channels per frame Companding selection on a per channel basis in TDM mode Input data port provides an additional input path to the DSP core configurable as either eight channels of I2S or serial data or as seven channels plus a single 20-bit wide syn- chronous parallel data acquisition port Supports receive audio channel data in I2S, left-justified sample pair, or right-justified mode Signal routing unit provides configurable and flexible connections between all DAI components, six serial ports, an input data port, two precision clock generators, three timers, 10 interrupts, six flag inputs, six flag outputs, and 20 SRU I/O pins Serial peripheral interface Master or slave serial boot through SPI Full-duplex operation Master-slave mode multimaster support Open drain outputs Programmable baud rates, clock polarities, and phases 3 Muxed Flag/IRQ lines 1 Muxed Flag/Timer expired line ROM based security features: JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multi- plier/divider ratios JTAG background telemetry for enhanced emulation features IEEE 1149.1 JTAG standard test access port and on-chip emulation Dual voltage: 3.3 V I/O, 1.2 V core Available in 136-ball BGA and 144-lead LQFP packages Lead free packages are also available

MAX1999EEI引脚说明： 8 - 32位和16 - 32位字包装选择可编程等待状态的选择：2至31个CCLK数字音频接口包括6个串行端口，两个前643时钟发生器，输入数据端口， 3可编程定时器和一个信号路由单元串行端口提供：六双串口数据线，在高达50 Mbps的操作/为200兆赫的每个数据行每个人都有一个时钟，帧同步的核心秒，和两个数据可以作为任何一个接收器或发射器对左对齐和I2S配对样本的支持下，最多可同时接收或传送24个频道，每使用两个系列的I2S兼容立体声设备配置可编程方向线；港口的TDM通信接口，包括支持128个电话接口的TDM的渠道，如H.100/H.110支持多达12个的TDM流的支持下，每帧128个频道每个压缩扩展每通道的基础上选择在TDM模式输入数据端口提供了一个额外的输入路径的DSP核心配置为I2S或串行数据或7加一个20位宽的SYN -异步的并行数据采集接口通道或8通道；支持接收通道I2S音频数据，左对齐样本对，或右对齐模式信号路由单元组件之间提供所有戴配置和灵活的连接，6个串行端口，一个输入数据端口，两个精密时钟发生器，3个定时器，10个中断，六旗投入，产出6个旗，20曼谷南南区域股的I / O管脚串行外设接口的硕士或奴隶通过SPI串行启动全双工运作主从模式多主机支持开漏输出可编程波特率，时钟极性和第三期合并调制旗/ IRQ线路1合并调制旗/定时器过期线光盘的防伪特征：JTAG的访问与64位受保护的关键允许内存内存可分配给程序访问控制的限制下对敏感地区有一个代码锁相环/遥测分比率为背景的JTAG仿真功能增强的IEEE 1149.1 JTAG标准测试访问端口的软件和硬件多钳各种各样和片上仿真双电压：3.3六/输出，可在1.2 V核心136球BGA封装和144引脚LQFP封装无铅封装，也可

TDA4864 Pinout: 8- to 32-bit and 16- to 32-bit word packing options Programmable wait state options: 2 to 31 CCLK Digital audio interface includes six serial ports, two pre- cision clock generators, an input data port, three programmable timers and a signal routing unit Serial ports provide: Six dual data line serial ports that operate at up to 50 Mbits/s for a 200 MHz core on each data line each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair Left-justified sample pair and I2S support, programmable direction for up to 24 simultaneous receive or transmit channels using two I2S compatible stereo devices per serial port TDM support for telecommunications interfaces including 128 TDM channel support for telephony interfaces such as H.100/H.110 Up to 12 TDM stream support, each with 128 channels per frame Companding selection on a per channel basis in TDM mode Input data port provides an additional input path to the DSP core configurable as either eight channels of I2S or serial data or as seven channels plus a single 20-bit wide syn- chronous parallel data acquisition port Supports receive audio channel data in I2S, left-justified sample pair, or right-justified mode Signal routing unit provides configurable and flexible connections between all DAI components, six serial ports, an input data port, two precision clock generators, three timers, 10 interrupts, six flag inputs, six flag outputs, and 20 SRU I/O pins Serial peripheral interface Master or slave serial boot through SPI Full-duplex operation Master-slave mode multimaster support Open drain outputs Programmable baud rates, clock polarities, and phases 3 Muxed Flag/IRQ lines 1 Muxed Flag/Timer expired line ROM based security features: JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multi- plier/divider ratios JTAG background telemetry for enhanced emulation features IEEE 1149.1 JTAG standard test access port and on-chip emulation Dual voltage: 3.3 V I/O, 1.2 V core Available in 136-ball BGA and 144-lead LQFP packages Lead free packages are also available

TDA4864引脚说明： 8 - 32位和16 - 32位字包装选择可编程等待状态的选择：2至31个CCLK数字音频接口包括6个串行端口，两个前643时钟发生器，输入数据端口， 3可编程定时器和一个信号路由单元串行端口提供：六双串口数据线，在高达50 Mbps的操作/为200兆赫的每个数据行每个人都有一个时钟，帧同步的核心秒，和两个数据可以作为任何一个接收器或发射器对左对齐和I2S样本对支持，最多可同时接收或传送24个频道，每使用两个系列的I2S兼容立体声设备配置可编程方向线；港口的TDM通信接口，包括支持128个电话接口的TDM的渠道，如H.100/H.110支持多达12个的TDM流的支持下，每帧128个频道每个压缩扩展每通道的基础上选择在TDM模式输入数据端口提供了一个额外的输入路径的DSP核心配置为I2S或串行数据或7加一个20位宽的SYN -异步的并行数据采集接口通道或8通道；支持接收通道I2S音频数据，左对齐样本对，或右对齐模式信号路由单元组件之间提供所有戴配置和灵活的连接，6个串行端口，一个输入数据端口，两个精密时钟发生器，3个定时器，10个中断，六旗投入，产出6个旗，20曼谷南南区域股的I / O管脚串行外设接口的硕士或奴隶通过SPI串行启动全双工运作主从模式多主机支持开漏输出可编程波特率，时钟极性和第三期合并调制旗/ IRQ线路1合并调制旗/定时器过期线光盘的防伪特征：JTAG的访问与64位受保护的关键允许内存内存可分配给程序访问控制的限制下对敏感地区有一个代码锁相环/分比率背景遥测的JTAG仿真功能增强的IEEE 1149.1 JTAG标准测试访问端口软件和硬件多钳各种各样和片上仿真双电压：3.3六/输出，可在1.2 V核心136球BGA封装和144引脚LQFP封装无铅封装，也可

与串行连接相关的网络解释 [注：此内容来源于网络，仅供参考]

CLK：时钟信号

由VP-0659记录驱动板传送过来的串行数据信号(SIN),时钟信号(CLK),选通信号(STB),分别通过这十二片MSI块驱动热敏元件各工作. 经仔细检查发现电路板上串行数据输人信号(SIN)到MSI片的连接上有轻微裂痕,经处理焊接后,故障排除,

DTE：终端设备

通过 RS-232-C 串行连接进行连接的两种硬件中的一种,另一种是"数据终端设备"(DTE) 设备. DCE 是一种中间设备,它通常在将 DTE 的输入发送给接收者之前先进行转换. 例如,调制解调器是一个 DCE,它先调制来自微型计算机 (DTE) 的数据,

RAS：远程访问服务

于强壮的红外通讯的"红外线数据协会"(IrDA)传输层用于串行连接网络的"点对点协议"(PPP)和"串行线路接口协议"(SLIP)通过网络驱动程序接口规范(NDIS)支持局域网通过调制解调器对远程文件系统连接的"远程访问服务"(RAS)客户

Serial Interface：串行接口

路由器通过接口在物理上把处于不同逻辑地址的网络连接起来. 这些网络的类型可以相同,也可以不同. 路由器的一些接口是ISDN接口,串行接口(Serial Interface)它们通常将路由器链接到广域网链路上,还有其他一些局域网接口(LAN接口)

Connectivity: Serial interface：连接:串行接口

Compatibility: PC USB 相容性 :个人电脑的USB | Connectivity: Serial interface 连接:串行接口 | Continuous Shooting Speed: 1.2 连续拍摄速度: 1.2

Serial Line Internet Protocol, SLIP：串列线联网协定

"serial interface","串行界面接口" | "Serial Line Internet Protocol (SLIP)","串列线联网协定" | "serial port","串行连接埠"

USB：通用串行总线

8月6日,Epson宣称开发出了"通用串行总线"(USB)端口"直接打印"技术,即只需通过USB端口直接将数码相机和打印机相连接直接打印出照片的技术.

overrange：超范围

通常这相需要100~200个时钟脉冲,但是在超范围(OVERRANGE)转换后,则需要6200个脉冲. 1.2与单片机系统的串行连接在ICL7135与单片机系统进行连接时,如果使用ICL7135的并行采集方式,则不但要连接BCD码数据输出线,又要连接BCD码数据的位驱动信号输出端,

time of day：日时间

支持当日时间(time of day)同步;串行RapidIO (SRIO)协议标准可轻松满足以上大部分要求,甚至超出这些要求的标准因此,串行RapidIO已成为无线通信基础设备中用于数据层(data plane)互连的主流连接技术SRIO网络建立在两个"基本模块"基础之上:端点设备(Endpoint)和交换设备(Switch)端点设备负责收发数据包,

time of day：当日时间

支持当日时间(time of day)同步;串行RapidIO (SRIO)协议标准可轻松满足以上大部分要求,甚至超出这些要求的标准因此,串行RapidIO已成为无线通信基础设备中用于数据层(data plane)互连的主流连接技术SRIO网络建立在两个"基本模块"基础之上:端点设备(Endpoint)和交换设备(Switch)端点设备负责收发数据包,