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reprogrammable相关的网络例句

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We adopted the AT89C55 which is compatible with MCS-51 products entirely, except the Host controller SL811HS. AT89C55 has 20K bytes of in-system reprogrammable flash memory. So we neednt to extend the RAM and simplify the hardware.

在器件选择上,除了采用具有主机控制器功能的SL811HS芯片外,其核心芯片采用的是与MCS-51完全兼容的AT89C55,它具有20K的FLASH,不必片外扩展ROM,简化了硬件电路。

Eatures · Compatible with MCS-51 Products · 2K Bytes of Reprogrammable Flash Memory – Endurance: 1,000 Write/Erase Cycles · 2.7V to 6V Operating Range · Fully Static Operation: 0 Hz to 24 MHz · Two-Level Program Memory Lock · 128 x 8-Bit Internal RAM · 15 Programmable I/O Lines · Two 16-Bit Timer/Counters · Six Interrupt Sources · Programmable Serial UART Channel · Direct LED Drive Outputs · On-Chip Analog Comparator · Low Power Idle and Power Down Modes Description The AT89C2051 is a low-voltage, high-performance CMOS 8-bit microcomputer with 2K Bytes of Flash programmable and erasable read only memory.

eatures ·兼容MCS - 51的产品·及2k字节的编程快闪记忆体-耐力: 1 000写/擦除周期·在2.7 V至6 V的操作范围·完全静态的运作: 0 Hz至24兆赫·两个层次的程式记忆体锁· 128 × 8位内部RAM · 15个可编程I / O线·两个16位定时器/计数器· 6中断源·可编程串行UART的频道·直接驱动LED产出·单晶片模拟比较·低功耗的闲置和掉电模式描述该AT89C2051的是一个低电压,高性能的CMOS 8位微机与及2k字节的Flash可编程和可擦除唯读记忆体。

The real2time target t rack processing system is designed which is const ruc2 ted by t he high performance DSP chip set TMS320C6416 as the core digital p rocessor , t he huge rep rogrammable logic chip set CPLD as t he system logic cont rol and the field reprogrammable array FPGA as t he image p reprocessing chip set to sampled video digital image.

为了解决算法复杂性及满足工程实时性,设计了以高性能的DSP 芯片TMS320C6416 为核心处理器,结合大规模可编程逻辑器件 CPLD 进行逻辑控制以及现场可编程门阵列FPGA 对采集的视频数字图像做预处理的实时目标识别跟踪处理平台。

ReProgrammable ROM?

可重编程只读存储器

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