查询词典 random access memory

There is daytime access to our award-winning library; research resources include access to other University of London libraries, the British Library and the British Museum; research students are eligible to apply for an Overseas Research Student award; a number of College studentships for doctoral and research students are also available; research students and their supervisors meet at mutually convenient times; many programmes have evening tuition, leaving the day free to combine directed study with other activities; full computing facilities and support; access to University of London accommodation services; College located at heart of academic London, 5 minutes from the British Museum.

设施白天学生可使用位於校内且曾荣获殊荣的图书馆，可用的研究资源还包括所有伦敦大学的图书馆，大英图书馆和大英博物馆；研究生皆有资格角逐海外研究生奖和奖助学金。研究生与他们的助教定期碰面；许多课程有晚间的加强辅导，白天则可运用於上课和其他的活动。学生有权使用伦敦大学的住宿服务和完备的电脑设备与协助。学校位於伦敦学术中心，距大英博物馆仅五分钟距离。

Due to support DMA (DirectMemory Access: Direct Memory Access) mode, it has good prospects for development.

由于支持 DMA （ DirectMemory Access ：直接内存存取）模式，因此具有很好的发展前景。

Note that direct access is not the same as direct memory access.

注意：直接访问并不等同于直接内

TL084MJ Pinout: 3.3V Operation with 5V Tolerant Buffers ACPI 1.1, PC99/PC2001 Compliant LPC Interface with Clock Run Support Serial IRQ Interface Compatible with Serialized IRQ Support for PCI Systems 15 Direct IRQs Four 8-Bit DMA Channels ACPI SCI Interface nSMI Shadowed write only registers Internal 64K Flash ROM Programmed From Direct Parallel Interface, 8051, or LPC Host 2k-Byte Lockable Boot Block Can be Programmed Without 8051 Intervention Three Power Planes Low Standby Current in Sleep Mode Intelligent Auto Power Management for Super I/O ACPI Embedded Controller Interface Configuration Register Set Compatible with ISA Plug-and-Play Standard (Version 1.0a) High-Performance Embedded 8051 Keyboard and System Controller Provides System Power Management System Watch Dog Timer 8042 Style Host Interface Supports Interrupt and Polling Access 256 Bytes Data RAM On-Chip Memory-Mapped Control Registers Access to RTC and CMOS Registers Up to 16x8 Keyboard Scan Matrix Two 16 Bit Timer/Counters Integrated Full-Duplex Serial Port Interface Eleven 8051 Interrupt Sources Thirty-Two 8-Bit, Host/8051 Mailbox Registers Thirty-six Maskable Hardware Wake-Up Events Fast GATEA20

TL084MJ引脚说明： 3.3V工作电压为5V容错缓冲器的ACPI 1.1，PC99/PC2001符合LPC接口与时钟运行支持-兼容串行接口与串行的IRQ IRQ的支持PCI系统- 15直接的IRQ - 4个8位DMA通道- ACPI的SCI接口- nSMI -阴影只写寄存器内部的64K的Flash ROM -直接从程序并行接口，8051，还是LPC主机-的2K字节可锁定引导块-可在不干预程序8051三力飞机-低待机电流在休眠模式-智能型自动电源管理的超级I / O的ACPI嵌入式控制器接口配置寄存器设置兼容的ISA拆开的播放标准（版本1.0a）高性能嵌入式8051键盘和系统控制器-提供系统电源管理-系统监视狗定时器- 8042型主机接口-支持中断和轮询访问- 256字节数据RAM -片上存储器映射控制寄存器-获取实时时钟和CMOS寄存器-最多16x8矩阵键盘扫描- 2个16位定时器/计数器-综合全双工串行接口- 11个中断源8051 - 32个8位，Host/8051邮箱寄存器- 36个可屏蔽硬件唤醒事件-快速GATEA20

These parallel access properties can reduce the memory system's average data access time.

本文在对高速缓存系统结构进行深入分析的基础上，把XOR斜排存储映射方法应用于数据高速缓存的存储映射中。

Several problems are resolved in the system, such as the data access in the memory, parallel file access from disk, and the replacement of file data.

解决了并行文件访问的难点：内存中数据的读写，并行化磁盘读写和文件数据的替换，性能测试表明在多用户并行处理的环境中，Parfsnow++有效地提高了系统性能，特别是在文件数据的共享，文件数据的替换，以及使用大容量的统一内存对文件数据的存取等方面。

The controller uses the data write buffer to reduce the data access waiting time, and employs the two ways of duo channels instruction pre-fetch buffer to decrease the fetching instruction waiting time and increase the instruction pre-fetch buffer hit rate. Meanwhile, to reduce the waiting time aroused by page miss of SDRAM, a four ways of on chip stack memory is introduced. Compared with traditional controller through experiments the novel SDRAM controller gets a high reduction up to 63% in access waiting time and 64% in page miss.

该控制器采用数据写缓存方式降低了数据在存取内存时的等待时间；并引入了两组双通道预取指令缓冲器，每组双通道都用以减少取指令时的等待时间，采用两组的结构是为了增加指令预取的命中率；同时还使用了四路组关联的片上堆栈存储器来降低SDRAM的页失效频率，从而降低了因页失效而需要等待的时钟周期。

The rule is simply that any access to the contents of a memory location requires square brackets around the address, and any access to the address of a variable doesn't.

这一规则很简单，就是对内存中存贮的任何内容的访问都要在地址上加方括号［］，其它对变量地址的访问都是不允许的。

It allows one base register to be used to access a number of memory locations which are in the same area of memory.

采用这种模式可以使用一个基址寄存器来访问位于同一区域的多个存储器单元。

A FLASH Direct Memory Access technique has been adopt for high-speed data transport between FLASH memory and data buffer.

研究并实现了FLASH存储器的直接存储访问控制技术，极大地提高了数据存取速度。

They have quite a lot of work to do.

他们有许多工作要做。

Let us give you a more elaborate example of this process.

让我们给你这个过程的更多的详细例子。