查询词典 clock

If you want to modify the clock, pressure Settings button to display window, input zero - 23:59 at the score (e.g., at about 3:30 p.m., second automatic reset input 1530, set the clock in 24 hours, and then press enter) system clock.

若要修改时钟值，压设置键显示窗口在闪烁，输入0-23点59分的时分值（如下午3点30分输入1530，秒自动清零，设置时钟时按24小时制输入），然后压时钟键即可。

The STK730-080 is a zero delay buffer that distributes a differential clock input pair to ten differential pairs of clock outputs (Y[0:9], Y[0:9]) and one differential pair feedback clock outputs .

该STK730 - 080是一种零延迟缓冲器，差分时钟分配一个输入对，以10的时钟输出（是[0时09]， [0点09]）和一个差分对的差分对时钟输出反馈（FBOUT，FBOUT）。

Finally, there is a cuckoo clock: according to written records, approximately 164 years with a pair of brothers named ESH invented the first block of FireWire world resting clock, which is the predecessor of a cuckoo clock, and later in 1750, settle an old francs.

最后是咕咕钟：根据记载，大约在1640年的时候，有一对名叫库兹的兄弟发明了第一座世界上最早问世的木架钟，这是咕咕钟的前身，后来在1750年时，一位法朗安顿。

Kettle cleverly bellows theory, design, can be issued for assignment of the clock and the song of the cuckoo is similar to, and completion of the worlds first cuckoo clock, a cuckoo clock industry since then has grown rapidly.

凯特尔先生巧妙地用风箱原理，设计出让钟可以发出与布谷鸟相似的歌声，而完成了世界上第一座咕咕钟，咕咕钟业自此迅速发展。

By utilizing the cross-gain modulation effect and the period-one oscillation harmonic frequency-locked in an optically injected semiconductor laser, we can extract the wavelength conversional individual channel optical clock from the optical-time-division-multiplexing signal. In a FP-LD, we numerically simulate the extraction of 20 GHz optical clock at 1550 nm from the 2×20 Gb/s OTDM signal at 1555 nm, and experimentally obtain the -105 dBc/Hz phase noise frequency division clock of 12.36 GHz to 6.18 GHz with simultaneous wavelength conversion from 1550.24 nm to 1545.91 nm.

采用一个FP半导体激光器作为全光分路时钟提取及波长转换器，数值模拟实现了从波长为1555 nm、速率为2×20 Gb/s的光时分复用信号中提取出波长转换为1550 nm、重复频率为20 GHz的分路光时钟，实验完成了从波长为1550.24 nm、重复频率为12.36 GHz光脉冲信号中提取出相位噪声为-105 dBc/Hz的波长为1545.91 nm、重复频率6.18 GHz的分频光时钟。

Clock sources are 508 kHz and 2 kHz. Both of these clock sources aresynchronized to the main system AHB bus clock.

时钟资源是508KHZ和2KHZ，这两个时钟资源都与主要系统AHB总线时钟同步。

To support these clock rates, a reasonable solution is to clock the ADC and DAC at a fixed master clock rate and perform sample rate conversion completely in digital domain.

为了支援这些标准，比较合理的作法是让类比转数位和数位转类比转换器工作在固定的频率，利用数位的作法改变取样频率以支援不同的通讯协定。

During 6:00-10:00 o'clock period, climbing of photosynthetic rate P(subscript n was primarily caused by photosynthetic active radiation, leaf temperature, relative humid. Descending photosynthetic rate P(subscript n from 10:00 o'clock to 14:00 o'clock, especially "middy depression" was mostly caused by stomata factor.

早晨6：00-10：00期间，光合速率的上升主要是光合有效辐射、温度和相对湿度造成的。10：00-14：00期间，光合速率的降低，尤其是"午休"期间的下降，气孔因素是主要限制因子。

MAX1999EEI Pinout: 8- to 32-bit and 16- to 32-bit word packing options Programmable wait state options: 2 to 31 CCLK Digital audio interface includes six serial ports, two pre- cision clock generators, an input data port, three programmable timers and a signal routing unit Serial ports provide: Six dual data line serial ports that operate at up to 50 Mbits/s for a 200 MHz core on each data line each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair Left-justified sample pair and I2S support, programmable direction for up to 24 simultaneous receive or transmit channels using two I2S compatible stereo devices per serial port TDM support for telecommunications interfaces including 128 TDM channel support for telephony interfaces such as H.100/H.110 Up to 12 TDM stream support, each with 128 channels per frame Companding selection on a per channel basis in TDM mode Input data port provides an additional input path to the DSP core configurable as either eight channels of I2S or serial data or as seven channels plus a single 20-bit wide syn- chronous parallel data acquisition port Supports receive audio channel data in I2S, left-justified sample pair, or right-justified mode Signal routing unit provides configurable and flexible connections between all DAI components, six serial ports, an input data port, two precision clock generators, three timers, 10 interrupts, six flag inputs, six flag outputs, and 20 SRU I/O pins Serial peripheral interface Master or slave serial boot through SPI Full-duplex operation Master-slave mode multimaster support Open drain outputs Programmable baud rates, clock polarities, and phases 3 Muxed Flag/IRQ lines 1 Muxed Flag/Timer expired line ROM based security features: JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multi- plier/divider ratios JTAG background telemetry for enhanced emulation features IEEE 1149.1 JTAG standard test access port and on-chip emulation Dual voltage: 3.3 V I/O, 1.2 V core Available in 136-ball BGA and 144-lead LQFP packages Lead free packages are also available

MAX1999EEI引脚说明： 8 - 32位和16 - 32位字包装选择可编程等待状态的选择：2至31个CCLK数字音频接口包括6个串行端口，两个前643时钟发生器，输入数据端口， 3可编程定时器和一个信号路由单元串行端口提供：六双串口数据线，在高达50 Mbps的操作/为200兆赫的每个数据行每个人都有一个时钟，帧同步的核心秒，和两个数据可以作为任何一个接收器或发射器对左对齐和I2S配对样本的支持下，最多可同时接收或传送24个频道，每使用两个系列的I2S兼容立体声设备配置可编程方向线；港口的TDM通信接口，包括支持128个电话接口的TDM的渠道，如H.100/H.110支持多达12个的TDM流的支持下，每帧128个频道每个压缩扩展每通道的基础上选择在TDM模式输入数据端口提供了一个额外的输入路径的DSP核心配置为I2S或串行数据或7加一个20位宽的SYN -异步的并行数据采集接口通道或8通道；支持接收通道I2S音频数据，左对齐样本对，或右对齐模式信号路由单元组件之间提供所有戴配置和灵活的连接，6个串行端口，一个输入数据端口，两个精密时钟发生器，3个定时器，10个中断，六旗投入，产出6个旗，20曼谷南南区域股的I / O管脚串行外设接口的硕士或奴隶通过SPI串行启动全双工运作主从模式多主机支持开漏输出可编程波特率，时钟极性和第三期合并调制旗/ IRQ线路1合并调制旗/定时器过期线光盘的防伪特征：JTAG的访问与64位受保护的关键允许内存内存可分配给程序访问控制的限制下对敏感地区有一个代码锁相环/遥测分比率为背景的JTAG仿真功能增强的IEEE 1149.1 JTAG标准测试访问端口的软件和硬件多钳各种各样和片上仿真双电压：3.3六/输出，可在1.2 V核心136球BGA封装和144引脚LQFP封装无铅封装，也可

TDA4864 Pinout: 8- to 32-bit and 16- to 32-bit word packing options Programmable wait state options: 2 to 31 CCLK Digital audio interface includes six serial ports, two pre- cision clock generators, an input data port, three programmable timers and a signal routing unit Serial ports provide: Six dual data line serial ports that operate at up to 50 Mbits/s for a 200 MHz core on each data line each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair Left-justified sample pair and I2S support, programmable direction for up to 24 simultaneous receive or transmit channels using two I2S compatible stereo devices per serial port TDM support for telecommunications interfaces including 128 TDM channel support for telephony interfaces such as H.100/H.110 Up to 12 TDM stream support, each with 128 channels per frame Companding selection on a per channel basis in TDM mode Input data port provides an additional input path to the DSP core configurable as either eight channels of I2S or serial data or as seven channels plus a single 20-bit wide syn- chronous parallel data acquisition port Supports receive audio channel data in I2S, left-justified sample pair, or right-justified mode Signal routing unit provides configurable and flexible connections between all DAI components, six serial ports, an input data port, two precision clock generators, three timers, 10 interrupts, six flag inputs, six flag outputs, and 20 SRU I/O pins Serial peripheral interface Master or slave serial boot through SPI Full-duplex operation Master-slave mode multimaster support Open drain outputs Programmable baud rates, clock polarities, and phases 3 Muxed Flag/IRQ lines 1 Muxed Flag/Timer expired line ROM based security features: JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multi- plier/divider ratios JTAG background telemetry for enhanced emulation features IEEE 1149.1 JTAG standard test access port and on-chip emulation Dual voltage: 3.3 V I/O, 1.2 V core Available in 136-ball BGA and 144-lead LQFP packages Lead free packages are also available

TDA4864引脚说明： 8 - 32位和16 - 32位字包装选择可编程等待状态的选择：2至31个CCLK数字音频接口包括6个串行端口，两个前643时钟发生器，输入数据端口， 3可编程定时器和一个信号路由单元串行端口提供：六双串口数据线，在高达50 Mbps的操作/为200兆赫的每个数据行每个人都有一个时钟，帧同步的核心秒，和两个数据可以作为任何一个接收器或发射器对左对齐和I2S样本对支持，最多可同时接收或传送24个频道，每使用两个系列的I2S兼容立体声设备配置可编程方向线；港口的TDM通信接口，包括支持128个电话接口的TDM的渠道，如H.100/H.110支持多达12个的TDM流的支持下，每帧128个频道每个压缩扩展每通道的基础上选择在TDM模式输入数据端口提供了一个额外的输入路径的DSP核心配置为I2S或串行数据或7加一个20位宽的SYN -异步的并行数据采集接口通道或8通道；支持接收通道I2S音频数据，左对齐样本对，或右对齐模式信号路由单元组件之间提供所有戴配置和灵活的连接，6个串行端口，一个输入数据端口，两个精密时钟发生器，3个定时器，10个中断，六旗投入，产出6个旗，20曼谷南南区域股的I / O管脚串行外设接口的硕士或奴隶通过SPI串行启动全双工运作主从模式多主机支持开漏输出可编程波特率，时钟极性和第三期合并调制旗/ IRQ线路1合并调制旗/定时器过期线光盘的防伪特征：JTAG的访问与64位受保护的关键允许内存内存可分配给程序访问控制的限制下对敏感地区有一个代码锁相环/分比率背景遥测的JTAG仿真功能增强的IEEE 1149.1 JTAG标准测试访问端口软件和硬件多钳各种各样和片上仿真双电压：3.3六/输出，可在1.2 V核心136球BGA封装和144引脚LQFP封装无铅封装，也可

Graf, without question, is the greatest women's player in history.

格拉芙，现在，毫无疑问是女子网坛历史上最伟大的选手。

If not, you will have to look around at all your important data.

如果没有，您将需要检查所有的重要数据。