- 更多网络例句与栅漏相关的网络例句 [注：此内容来源于网络，仅供参考]
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A new circular rod leaky wave antenna with multi-layer dielectric gratings has been systematically and theoretically analyzed with the rigorous mode matching method to provide the gist and guidance for the design of the leaky wave antenna.
对多层圆形介质栅漏波天线进行系统的理论分析，为该天线的精确设计提供必要的依据和指导原则。
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It can also be applied to different voltage range, if the subcircuit model uses different types of FET models.
同时，根据不同沟道区域的饱和原理，采用不同的模型与参数进行模拟，使子电路适用于不同栅压和漏压。
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The invention relates to an organic thin-film transistor of three-layer composite film insulated gate which comprises a substrate (1), a metal electrode (2), a organic semiconductor layer (6), a source/leakage electrode; and also comprises: a low dielectric constant polymer layer (3), a high dielectric constant oxide layer (4), a low dielectric constant polymer layer (5), three-layer composite film insulated gate is composed of the (3) layer, the (4)layer and the (5) layer.
本发明涉及三层复合膜绝缘栅的有机薄膜晶体管，包括衬底(1)，金属电极(2)，有机半导体(6)层，源/漏电极(7)；还包括：低介电常数聚合物层(3)，高介电常数氧化物层(4)，低介电常数聚合物层(5)，所述的(3)、(4)和(5)层构成三层复合膜绝缘栅。
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Thus, the output will always be driven by a single transistor, either P- channel or N-channel. Since they are as closely matched as possible, the output resistance of the gate will always be the same, and signal behavior is therefore more predictable. Fig. 3.4 CMOS NAND gate One of the main problems with CMOS gates is their speed. They cannot operate very quickly, because of their inherent input capacitance. B-series devices help to overcome these 24 Lesson 3 CMOS Logic Circuit 25 limitations to some extent, by providing uniform output current, and by switching output states more rapidly, even if the input signals are changing more slowly. Note that we haven't gone into all of the details of CMOS gate construction here. For example, to avoid damage caused by static electricity, different manufacturers developed a number of input protection circuits to prevent input voltages from becoming too high. [3] However, these protection circuits don't affect the logical behavior of the gates, so we won't go into the details here. New Words and Phrases 1. CMOS abbr.
略语互补金属氧化物半导体(complementary metallic oxide semiconductor)逻辑，逻辑学，逻辑性，推理方法补充的，补足的，互补的电池供电的门电路，逻辑门，闸门，控制栅，大门，通道，门口，入口伏特，环骑，闪避基础的，基本的，主要的基本原则，基本原理增强型金属氧化物半导体场效应晶体管(metallic oxide semiconductor field effect transistor)反相器，反用换流器，变极器来源，水源，消息来源，原始资料，发起者源，源极排水沟，消耗，排水漏极排出，喝干，耗尽排水，流干，耗尽相同的，相配的，匹配的匹配有效地，有力地，事实上，实际上无限的东西无穷大无穷的，无限的，无数的，极大的接地的正向偏置的，正偏的或非 25 2。
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A new SOI LDMOS with folded silicon is proposed,in which the silicon substrate surface is trenched to form a folded shape from the channel to the drain electrode and the gate is extended to the drain.
提出了一种具有折叠硅表面SOI-LDMOS新结构。它是将硅表面从沟道到漏端的导电层刻蚀成相互排列的折叠状，且将栅电极在较薄的场氧化层上一直扩展到漏端。
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A series of slow drain current recovery transients at different gate biases after a short-term stress are observed in an AlGaN/GaN HEMT. As the variation of the time constants of the transients is small, the working trap is determined to be electronic.
观察了AlGaN/GaN HEMT器件在短期应力后不同栅偏置下的一组漏极电流瞬态，发现瞬态的时间常数随栅偏压变化很小，据此判断这组瞬态由电子陷阱的释放引起。
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The invention discloses a high-voltage P-type metal oxide semiconductor, including a P-type substrate, a deep N-well is arranged on the P-type substrate, an N-well drift region and a P-type drift region are arranged on the deep N-well, an N-type contact hole, a P-type source and a field oxide layer are arranged on the N-well, a P-type drain and the field oxide layer are arranged on the P-type drift region; the invention is characterized in that the thickness a grid oxide layer part which is positioned above the N-well is smaller than the grid oxide layer part which is positioned above the P-type drift region and a thin grid oxide layer and a thick thin grid oxide layer are respectively formed accordingly.
本发明公开一种高压P型金属氧化物半导体管，包括P型衬底，在P型衬底上设有深N型阱，在深N型阱上设有N型阱和P型漂移区，在N型阱上设有N型接触孔、P型源及场氧化层，在P型漂移区上设有P型漏及场氧化层，其特征在于位于N型阱上方的栅氧化层部分的厚度小于位于P型漂移区上方的栅氧化层部分并由此分别形成薄栅氧化层和厚薄栅氧化层。
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The invention discloses a high-voltage N-type metal oxide semiconductor, including a P-type substrate, a P-well drift region and an N-type drift region are arranged on the P-type substrate, a P-type contact hole, an N-type source and a field oxide layer are arranged on the P-well, an N-type drain and the filed oxide layer are arranged on the N-type drift region; the invention is characterized in that the thickness a grid oxide layer part which is positioned above the P-well is smaller than the grid oxide layer part which is positioned above the N-type drift region and a thin grid oxide layer and a thick thin grid oxide layer are respectively formed accordingly, a P-type impurity injection region is arranged in the P-well, and the P-type impurity injection region is positioned below the thin grid oxide layer.
本发明公开一种高压N型金属氧化物半导体管，包括P型衬底，在P型衬底上设有P型阱和N型漂移区，在P型阱上设有P型接触孔、N型源及场氧化层，在N型漂移区上设有N型漏及场氧化层，其特征在于位于P型阱上方的栅氧化层部分的厚度小于位于N型漂移区上方的栅氧化层部分并由此分别形成薄栅氧化层和厚薄栅氧化层，在P型阱内设有P型杂质注入区且该P型杂质注入区位于薄栅氧化层的下面。
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The thin film transistor may include: a gate insulting layer; a gate electrode formed on the gate insulating layer; a channel layer formed on the gate insulating layer; and source and drain electrodes that contact the channel layer.
具体而言，薄膜晶体管可以包括：栅绝缘层；形成在栅绝缘层上的栅电极；形成在栅绝缘层上的沟道层；以及接触沟道层的源和漏电极。
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Polymer-based thin film transistors with poly(3-hexylthiophene)(P3HT) as semiconducting active layers were successfully fabricated on silicon substrates in air which was used as gate electrode, HfTiO film deposited by RF sputtering method was used as gate insulators, and gold metal was used as source and drain electrodes. The HfTiO surface was modified by using octadecyltrichlorosilane solution during fabrication process.
以高掺杂Si单晶片作为衬底且充当栅电极，采用磁控溅射法在硅片上沉积HfTiO薄膜作为栅介质层，聚三己基噻吩(P3HT)薄膜作为半导体活性层，金属Au作为源、漏电极，并采用十八烷基三氯硅烷对栅介质层表面修饰，在空气环境下成功地制备出聚合物薄膜晶体管。
- 更多网络解释与栅漏相关的网络解释 [注：此内容来源于网络，仅供参考]
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grid leak condenser：栅漏电容器
grid leak capacitor detector 栅漏电容检波器 | grid leak condenser 栅漏电容器 | grid leak detector 栅漏检波器
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grid leak and condenser detection：栅漏电容检波
栅漏 grid leak | 栅漏电容检波 grid leak and condenser detection | 栅漏偏压 grid leak bias
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grid leak：栅漏
grid current detection 栅极检波 | grid leak 栅漏 | grid modulation 栅极灯
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grid leak resistor：栅漏电阻
grid leak detector 栅漏检波器 | grid leak resistor 栅漏电阻 | grid lerk condenser 栅漏电容器
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grid leak resistor：栅漏
grid leak 栅漏 | grid leak resistor 栅漏 | grid plate capacitance 栅极 屏极电容
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grid leak detector：栅漏检波器
grid leak capacitor detector 栅漏电容检波器 | grid leak detector 栅漏检波器 | grid leak resistor 栅漏电阻
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grid leak modulation：栅漏调制
grid leak detector 栅漏检波器 | grid leak modulation 栅漏调制 | grid levelling 面水准测量,方格水准测量
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variable grid leak：可变栅漏
variable grid 变距栅网 | variable grid leak 可变栅漏 | variable head permeability test 变水头渗透试验
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leak tester：漏泄测试器
leakproof 防漏的,密封的 | leak tester 漏泄测试器 | leaky grid detector 栅漏检波器
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CdS：漏-源电容
FET提供了具有本征栅-漏电容(Cgd),栅-源电容(Cgs),以及漏-源电容(Cds)的跨导(Gm). 在小信号模型中,1-3这些参数(以及其他参数)确定了最大增益的最佳源极和漏极负载. 在非线性器件模型中,其确定了最大功率和线性负载. 传统上,