时钟频率

词组短语

clock rate · clock frequency

与时钟频率相关的网络例句 [注：此内容来源于网络，仅供参考]

In these two modes the DATA and CLK pins should not be clocked to reduce noise in the captured pressure or temperature data.

在这两个数据和时钟引脚不应时钟频率为减少捕获的压力和温度数据的噪音模式。

The maximum number of cycles is 135, requiring a clock rate of 1.08 MHz.

最大的时钟周期数为135，需要的时钟频率为1.08 MHz。

It's definitely unique and eye-catching clock which literally tells you the time unlike your standard digital clock.

这绝对是独特的和引人注目的时钟频率，这从字面上告诉你的时间不同，您的标准数字时钟。

The system can schedule at interrupt service level and thus responsive property of system is improved accordingly.

时钟作为操作系统的脉搏，是协调系统运作的一个重要依据，一般系统的时钟频率是固定的。

Functional Description The M6242 is designed for low skew clock distribution systems and supports clock frequencies up to 3 GHz.

功能描述M6242是专为低偏移时钟分配系统，并支持时钟频率高达3 GHz的。

Taking the high precision on chip RTC as the time base control unit and using genetic algorithms to search the best OSCCAL register value, it will make the on chip RC oscillator generate a high precision clock for the MCU. This methord can be used fast and real time, so the CPU will get a stable clock source.

以AVR片内高精度时钟单元RTC为时基控制单元，以标准时间内MCU定时器的计数值为控制目标，采用遗传控制策略搜索对应MCU理想时钟频率的OSCCAL寄存器最佳设置值，快速、准确地对RC振荡频率进行校准，为CPU提供具有高抗干扰特性的精确时钟。

The number of the frequency division of the method and the circuit structure thereof do not influence the highest frequency of the working circuit. The normal work of the frequency division circuit can be at a comparatively high clock frequency, and the clock frequency division can be realized in the manner of cascade connection of the frequency division circuit so that the scale of the circuit realization can be properly reduced.

本发明所述方法及其电路结构的分频数大小不影响电路工作的最高频率，可以使分频电路正常的工作在相对很高的时钟频率，而且可以通过分频电路级联的方式实现时钟分频，从而可以适当减小电路实现的规模。

In 1989, we familiar to ear 80486 chipses be released by the INTEL, the great place of this kind of chip lies in the boundary that it broke 1,000,000 transistors actually, integrating 1,200,000 transistors.80486 clock frequencies raise a 33 MHzs, 50 MHzs gradually from the 25 MHzs.80486 is 80386 help processor with mathematics,80387 and 1 high speed of 8 KBses saves an integration slowly in a chip, and in the 80 X86 the serieses for the very first time adopted a RISC technique, can carry out an instruction in a clock period.

1989年，我们大家耳熟能详的80486芯片由INTEL推出，这种芯片的伟大之处就在于它实破了100万个晶体管的界限，集成了120万个晶体管。80486的时钟频率从25MHz逐步提高到33MHz、50MHz.80486是将80386和数学协处理器80387以及一个8KB的高速缓存集成在一个芯片内，并且在80X86系列中首次采用了RISC技术，可以在一个时钟周期内执行一条指令。

In addition to setting the clock frequency, the master must also configure the clock polarity and phase with respect to the data. Freescale's SPI Block Guide [1] names these two options as CPOL and CPHA respectively, and most vendors have adopted that convention.

除了设置时钟频率，主设备同样需要设置数据传输相关的时钟极性以及相位。freescale'sSPI的手册命名这分别以cpol以及cpha来标志时钟的极性以及相位，大部分的芯片厂商采用了这种协定。

The method and the telecommunication switching system are characterised in that the heterogeneous data is collated and serialised and the serialised data transmitted with a clock frequency which is a common whole number multiple of the clock frequencies of the collated heterogeneous data.

该方法和电信系统的特征在于：所述的不同种类的数据被组合和被串行化，该被串行化的数据利用一个时钟频率进行传输，该时钟频率是需要被组合的不同种类数据的时钟频率的整数公倍数。

与时钟频率相关的网络解释 [注：此内容来源于网络，仅供参考]

clock cycle：时钟周期

(1)时钟周期(clock cycle)的频率:8253/8254PIT的本质就是对由晶体振荡器产生的时钟周期进行计数,晶体振荡器在1秒时间内产生的时钟脉冲个数就是时钟周期的频率.

clock cycle clock rate：时钟周期 时钟频率

cartesian product 笛卡尔积 | clock cycle clock rate 时钟周期时钟频率 | coaxial cable 同轴电缆

clock pulse source：时钟脉冲源

clock pulse rate 时钟频率 | clock pulse source 时钟脉冲源 | clock rate 时钟频率

clock pulse source：时钟脉冲源iVJ中国学习动力网

clock pulse rate 时钟频率iVJ中国学习动力网 | clock pulse source 时钟脉冲源iVJ中国学习动力网 | clock rate 时钟频率iVJ中国学习动力网

clock pulse rate：时钟频率

clock frequency 时钟频率 | clock pulse rate 时钟频率 | clock pulse source 时钟脉冲源

clock pulse rate：时钟频率iVJ中国学习动力网

clock frequency 时钟频率iVJ中国学习动力网 | clock pulse rate 时钟频率iVJ中国学习动力网 | clock pulse source 时钟脉冲源iVJ中国学习动力网

Clock rate：时钟频率

263解码器,载荷类型( Payload Type)固定为34,时钟频率(Clock Rate)固定为90 000 (根据RFC1890修订版) . 电话RTP流处理模块伪代码如下:

Bus Clock Rate：总线时钟频率

Bus Circuits 总线电路 | Bus Clock Rate 总线时钟频率 | Bus Controller 总线控制器

main clock：主时钟

在这里需要区别一个概念:主时钟和主机时钟主时钟(main clock)是指输入主振荡器的时钟主机时钟(mck)指CPU的时钟频率. 主机时钟可以在4个时钟源中选择(时钟选择器)一个作为本身的时钟

master clock frequency：主时钟频率

master clock 母钟,主钟 | master clock frequency 主时钟频率 | master clock-pulse generator 主时钟脉冲发生器,母时钟脉冲发生器,母钟脉冲发生器