时钟周期

词组短语

clock cycle · clock period

与时钟周期相关的网络例句 [注：此内容来源于网络，仅供参考]

Because each clock cycle has both a high and a low state, after the first clock pulse, two LEDs will always be on—that is, LED 1, LED 1 and 2, LED 2 and 3, LED 3 and 4, and so on.

因为每个时钟周期都是高低电平状态，第一个时钟脉冲后，两个LED通常是亮的——也就是说，LED1，LED1和2，LED2和3，LED3和4，等等。

CPU clock speeds are measured in megahertz, or MHz, with each cycle known as a "clock tick."

CPU时钟速度单位是兆赫兹，或者是MHz，也就是每一周被称为"时钟周期"。

When metastability occurs the clock-to-out time can be extended beyond the register's nominal tCO time. The additional time beyond the tCO time for the output signal to settle to a known state is known as the settling time. The tMET of a synchronization register chain is the sum of all output slacks of the registers in the chain.

对于这段话，我的理解是： tMET 时间和 tCO 时间之和就是异步时钟域的亚稳态时间，如果这个时间大于目的时钟域的同步寄存器链的时序余量（大概是时钟周期减去它的建立时间和保持时间之和吧），那么这时候系统采到的信号一定是亚稳态。

On the design of algorithms, a novel exact hierarchical delay analysis method for general circuits is proposed; based on the sensitization theorem for sequential circuits, an exact minimizing clocking method is proposed; based on Boolean process, a waveform simulation method considering interconnecting delay for logic circuit and a parallel waveform simulation method are proposed; a new method that transforms bit-level waveform polynomial to word-level polynomial model is proposed; a multiple valued synthesis algorithm based on multiple valued Boolean process and a wire-centered delay synthesis policy are proposed, in which timing planning, floorplanning, wire planning and optimal clock skew in early design are considered; a two-layers channel routing method for minimizing crosstalk under grid mode is proposed; based on the transition numbers theorems for waveform polynomial, a new method for generation of test with noise effects is proposed.

算法设计方面，提出了一种精确的通用电路层次化延时分析方法；基于时序电路的敏化定理提出时序电路最小时钟周期精确确定方法；提出基于Boolean过程论的考虑互连延迟的逻辑电路波形模拟方法，在分析了波形模拟适合并行化基础上，进一步提出一种并行波形模拟算法；提出一种将位级电路波形多项式描述转化成字级多项式描述的新方法；提出一种基于多值Boolean过程的多值电路综合算法以及一种将前期设计定时规划、前期设计的布局规划和线网结构化方法及低偏移的时钟分配等技术相结合的面向互连延时的综合策略；提出一种串绕最小化的网格模式下的双层通道布线方法；从波形多项式描述跳变数的定理出发提出了一种考虑噪声效应的测试生成新方法。

In addition, an experimental system using C language is established, including modules such as representation of waveform polynomial, decision of path senstization, delay computing, clocking based on single-period sensitization, clocking based on multi-period sensitization, test generation considering noise and transformation from bit-level waveform polynomial to word-level polynomial model. They respectively used to test models and techniques proposed in this paper.

另外，：基于C语言本人设计开发了一个实验软件系统，该系统包括波形多J一贞式表示模块、敏化通路判定模块、延时计算模块、单周期敏化的最小时钟周期精确确定模块、多周期敏化的最小时钟周期确定方法模块、考虑噪声的测试生成模块和位级波形多项式描述转化成字级多项式描述模块，分别用于对本文各章中提出的自动化设计的模型和方法进行实验验证。

A new method that transforms bitlevel waveform polynomial to word-level polynomial model is given, allowing for simple composition This method offers an efficient way to determine whether two descriptions from different design levels are equivalent, so component reuse, synthesis and verification across design levels can be realized. In addition, an experimental system using C language is established, including modules such as representation of waveform polynomial, decision of path senstization, delay computing, clocking based on single-period sensitization, clocking based on multi-period sensitization, test generation considering noise and transformation from bit-level waveform polynomial to word-level polynomial model. They respectively used to test models and techniques proposed in this paper.

另外，基于C语言本人设计开发了一个实验软件系统，该系统包括波形多项式表示模块、敏化通路判定模块、延时计算模块、单周期敏化的最小时钟周期精确确定模块、多周期敏化的最小时钟周期确定方法模块、考虑噪声的测试生成模块和位级波形多项式描述转化成字级多项式描述模块，分别用于对本文各章中提出的自动化设计的模型和方法进行实验验证。

In 1989, we familiar to ear 80486 chipses be released by the INTEL, the great place of this kind of chip lies in the boundary that it broke 1,000,000 transistors actually, integrating 1,200,000 transistors.80486 clock frequencies raise a 33 MHzs, 50 MHzs gradually from the 25 MHzs.80486 is 80386 help processor with mathematics,80387 and 1 high speed of 8 KBses saves an integration slowly in a chip, and in the 80 X86 the serieses for the very first time adopted a RISC technique, can carry out an instruction in a clock period.

1989年，我们大家耳熟能详的80486芯片由INTEL推出，这种芯片的伟大之处就在于它实破了100万个晶体管的界限，集成了120万个晶体管。80486的时钟频率从25MHz逐步提高到33MHz、50MHz.80486是将80386和数学协处理器80387以及一个8KB的高速缓存集成在一个芯片内，并且在80X86系列中首次采用了RISC技术，可以在一个时钟周期内执行一条指令。

Pinout: C High-performance 32-bit RISC Architecture C High-density 16-bit Instruction Set C Leader in MIPS/Watt C Little-endian C Embedded ICE (In-circuit Emulation) 8-, 16- and 32-bit Read and Write Support 256K Bytes of On-chip SRAM C 32-bit Data Bus C Single-clock Cycle Access Fully Programmable External Bus Interface C Maximum External Address Space of 64M Bytes C Up to Eight Chip Selects C Software Programmable 8/16-bit External Data Bus Eight-level Priority, Individually Maskable, Vectored Interrupt Controller C Four External Interrupts, including a High-priority, Low-latency Interrupt Request 32 Programmable I/O Lines Three-channel 16-bit Timer/Counter C Three External Clock Inputs C Two Multi-purpose I/O Pins per Channel Two USARTs C Two Dedicated Peripheral Data Controller Channels per USART Programmable Watchdog Timer Advanced Power-saving Features C CPU and Peripheral Can be Deactivated Individually Fully Static Operation: C 0 Hz to 75 MHz Internal Frequency Range at VDDCORE = 1.8V, 85C 2.7V to 3.6V I/O Operating Range 1.65V to 1.95V Core Operating Range -40C to +85C Temperature Range Available in 100-lead TQFP Package

M5L8253P-5引脚说明： C型高性能32位RISC架构C高密度以MIPS /瓦C小端C十六位指令集C领袖嵌入式冰8 - 16 -位和32位的读写支持256K的片上SRAM的 32位数据总线C单时钟周期存取字节完全可编程的外部总线接口C最大的外部地址空间的64M字节多达8个C芯片选择C软件可编程8位外部数据总线8级优先级，独立可屏蔽，向量中断控制器C四外部中断，其中包括一个高优先级，低延迟中断要求32个可编程I / O口线三通道16位定时器/计数器C三个外部时钟输入C两多用途I / O引脚每通道2个通用同步C两专用外设数据控制器通道每个USART可编程看门狗定时器先进的节能特性 CPU和外设可停用独立全静态工作中：C 0 Hz至75 MHz的频率范围内的VDDCORE = 1.8，85℃2.7V到3.6VI / O的操作1.65V到1.95V范围核心工作电压范围在- 40C至+85 C温度范围内使用的100引脚TQFP封装

Compared with tranditional methods, it is not too optimistic or pessimistic, fit for the exact timing of high-speed circuit design. Anda retiming scheme based on the above method is also presented to optimize the timing behavior of sequential circuits.

同传统方法相比，本方法计算出的最小周期既能保证电路的正确计算，又不至于保守，而且能同时计算出组合逻辑部分的延迟；然后从时序电路的波形多项式出发，进一步给出了多周期敏化的最小时钟周期确定方法，适用于有苛刻定时要求的环境。

All the fuzzy inference are processed in parallel,and the highest speed is 1-mega per second.With convenient IO interface and reprogrammable rules.

PFLC有方便的输入输出接口和修改规则，其模糊推理过程是并行的，每时钟周期完成一次，最高时钟频率可达1MHz。

与时钟周期相关的网络解释 [注：此内容来源于网络，仅供参考]

clock cycle：时钟周期

(1)时钟周期(clock cycle)的频率:8253/8254PIT的本质就是对由晶体振荡器产生的时钟周期进行计数,晶体振荡器在1秒时间内产生的时钟脉冲个数就是时钟周期的频率.

clock cycle：脉冲周期

到达接收端的时间不同步,时钟脉冲相位差降低了信号沿到达的可预测性,如果时钟脉冲相位差太大,会在接收端产生错误的信号,如图1所示.传输线时延已经成为时钟脉冲周期(Clock Cycle)中的重要部分.

clock cycle：时钟(脉冲)周期

时钟脉冲相位差是指同时产生的两个时钟信号,到达接收端的时间不同步. 时钟脉冲相位差降低了信号沿到达的可预测性,如果时钟脉冲相位差太大,会在接收端产生错误的信号,如图l所示. 传输线时延已经成为时钟脉冲周期(Clock Cycle)中的重要部分.

clock cycle：同步脉冲周期

climatic pessimum气候恶劣期 | clock cycle同步脉冲周期 | clock period时钟周期

CLK:Clock Cycle：时钟周期

CISC:Complex Instruction Set Computing,复杂指令集计算机 | CLK:Clock Cycle,时钟周期 | CPU:Center Processing Unit,中央处理器

clock cycle clock rate：时钟周期 时钟频率

cartesian product 笛卡尔积 | clock cycle clock rate 时钟周期时钟频率 | coaxial cable 同轴电缆

CCT: Clock Cycle Time：时钟周期

cc-NUMA: cache-coherent non uniform memory access,连贯缓冲非统一内存寻址 | CCT: Clock Cycle Time,时钟周期 | CD ROM:Compact Disc Read Only Memory,只读光盘

CCT Clock Cycle Timer：时钟周期定时器

CCT Character Class Table 字符分类表 | CCT Clock Cycle Timer 时钟周期定时器 | CCT Connecting Circuit T T型连接电路

CCS Clock Cycle Start：时钟周期起始

CCS Civil Communication Service 民用通信服务 | CCS Clock Cycle Start 时钟周期起始 | CCS Collective Call Sign 集体呼叫信号

False Clocking：假时钟

串扰(Crosstalk)能够引起一个静态线在时钟周期内出现切换. 什么是假时钟(false clocking) 假时钟是指时钟越过阈值(threshold)无意识地改变了状态(有时在VIL 或VIH 之间). 通常由于过分的下冲(undershoot)或串扰(crosstalk)引起.