地址代码

词组短语

address code

与地址代码相关的网络例句 [注：此内容来源于网络，仅供参考]

In the following section, the realization mechanism of memory distribution and bootcode of Microcontroller AT91M40800 is introduced, and the memory distribution file is written in order to define the address mapping relationship of software code and data during loading and running.

在操作系统平台建立之后，文章研究了AT91M40800的内存分配以及启动代码的实现机制，并编写了scatter内存分配文件，以定义本系统软件代码和数据在程序加载和运行过程中的地址映射关系。

X60008EIS8-50 Pinout: In order to detect whether the boot block feature is set on or not, users can perform software command sequence: enter the product identification mode (see Command Codes for Identification/Boot Block Lockout Detection for specific code), and then read from address 7FFF2.

X60008EIS8-50引脚说明：为了检测是否启动区块功能或没有设置，用户可以进行软件的命令序列：输入产品识别模式（见识别/引导块锁定检测特定的代码指令代码），然后从地址7FFF2阅读。

Based on a lot of experiment results, a conclusion is drawn: comparing with other factors, the performance of branch handling strategy is the key limits of processor to exploit the instruction level parallelism existed in nonscientific code, cache miss have severe effect on superscalar processor's performance when it runs scientific code. Second, in order to reduce the branch penalty and improve the performance of superscalar processor, a new branch handling strategy—a classification based hierarchical branch handling strategy, CHBHS is proposed. It first expands the traditional processor architecture to support multiple condition code, conditional execution and Mbranch instruction, as a result, compiler can reduce the number of static conditional branch when the code is generated. Then, CHBHS tries to use the best suitable mechanism to deal with different branch base on their different behavior. CHBHS can predict the target address of unconditional branch, subroutine call and conditional branch by buffering their target address in branch target buffer, a newly proposed high efficient return address stack is used to reduce the penalty of subroutine return instruction, a new Counter Register Stack is also proposed to reduce the penalty of loop-closing branch to zero, and dynamic branch predictor is incorporate with branch target buffer to predict the outcome of conditional branch.

基于上述结论，为了尽量消除转移指令对处理器开发指令级并行性能力的影响，进一步提高处理器性能，在详尽分析目前已存在的转移处理策略的特点与局限性的基础上，首次提出了一种新的转移处理策略即基于分类的层次转移处理策略CHBHS(Classification Based Hierarchical Branch Handling Strategy)，它首先通过扩展传统的体系结构，支持多条件码、条件式执行及多分支转移技术，以使编译程序在进行代码生成时可尽量少生成条件转移指令，从而减少静态条件转移指令的数目；其次，基于不同的转移指令的行为不同这一事实，提出了对不同的转移指令采用不同的机制进行处理的思想，即对无条件转移指令和函数调用指令以及条件转移指令的目标地址，采用转移目标缓冲器来预测，对于函数返回指令，采用所提出一种的高效返回地址栈来预测其目标地址，对于大多数循环控制转移指令，采用所提出的Counter Register Stack来将其所可能带来的损失减少为0，对于其他的条件转移指令采用动态预测机制来预测其方向。

The invention provides a method for modifying ELF file format in multi-core architecture, which comprises the steps:(1) a user adds a parallel processing flag;(2) independent codes are loaded into different code segments in a ELF file;(3) the flag bit in the header of the ELF file is modified to mark a new ELF format;(4) the starting addresses of newly added segments are added in a new thread;(5) a loader of ELF format is modified;(6) a multi-thread program is executed on different cores; and (7) different thread results are set unifiedly in a main thread by a compiler.

本发明提供了一种多核体系结构下的ELF文件格式改造的方法。包括以下步骤：(1)用户添加并行处理标志；(2)把独立的代码装载进ELF文件中不同的代码段中；(3)修改ELF文件头中的标志位，来标识新的ELF格式；(4)增加新加的段在新线程中的起始地址；(5)修改ELF格式的装载器；(6)多线程程序在不同核上的执行；(7)不同线程结果的统一由编译器在主线程中进行设置。

Also, a Harvard architecture machine has distinct code and data address spaces: instruction address zero is not the same as data address zero.

同时，哈佛架构机拥有不同的代码和数据地址空间：指令的零地址和数据的零地址不是一回事。

This JMP is the unique thing about table-based n-way conditionals, and it really makes it easy to identify them while reversing.

否则，代码将进入一个无条件跳转，跳转到一个特殊的条件块中(图中汇编代码的第5行)请注意这句jmp的地址是由表的基址加上索引×4构成的。

Simple. Executable is analyzed, transformed, and an extra piece of code is attached which gets invoked instead of the original program. This piece is called a 'stub' and decompresses the image to its original location. Then it jumps to that original location.

简单，程序经过分析，转换，然后将一段代码插入程序代替原程序首先被调用，这个被称为'stub'，解压源程序到原地址，然后它再跳到原地址。

Simple. Executable is analyzed, transformed, and an extra piece of code is attached which gets invoked instead of the original program. Thispiece is called a 'stub' and decompresses the image to its original location. Then it jumps to that original location.

简单，程序经过分析，转换，然后将一段代码插入程序代替原程序首先被调用，这个被称为'stub'，解压源程序到原地址，然后它再跳到原地址。

The combination of the code plug's three pre-coded frame location bits and the address codeword's 18 address bits provides over two million different assignable codes.

代码的插件的前三个结合位编码帧的位置和地址码字的18位地址提供200多万种不同的分配代码。

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与地址代码相关的网络解释 [注：此内容来源于网络，仅供参考]

ASP：代码

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DST：目的地址

即使微处理器的内部寄存器之间的访问用1字节指令代码描述,当描述存储器或I/O地址(目的地址(dst)或源地址(src))时,指令代码至少为2个字节. 第1个字节称为操作码,并且当微处理器读取该操作码时,操作过程即为操作码的获取.

four address instruction：四地址指令

four address code 四地址代码 | four address instruction 四地址指令 | four wire channel 四线信道

Four Address：四地址制

four probe method 四探针法 | four-address 四地址制 | four-address code 四地址代码

four address code：四地址代码

foundation architecture 基础结构 | four address code 四地址代码 | four address instruction 四地址指令

multiple address code：多地址代码

Multiple Access Computers 多路存取计算机,多输入(通路)计算机 | Multiple Address Code 多地址代码 | Multiple Address Computer 多地址计算机

multiple address code：多地址代码,多地址码

multiple-activity process chart 多样活动过程图 | multiple-address code 多地址代码,多地址码 | multiple-address computer 多地址计算机

single address code：一地址代码

single address 单地址的 | single address code 一地址代码 | single address instruction 单地址指令

Single Address：单地址的

single 单的 | single address 单地址的 | single address code 一地址代码

Two Address：二地址的

twisted torus 挠环面 | two address 二地址的 | two address code 二地址代码