- 更多网络例句与主时钟相关的网络例句 [注：此内容来源于网络，仅供参考]
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While switching main clock (regardless of high freq to low freq or on the other hand), adding 6 instructions delay is required.
虽然切换主时钟另一方面，加入6指示延迟的需要。
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In this paper,the design and implement of the best master clock algorithm of IEEE1588 are analyzed in detail.
针对 IEEE1588的最佳主时钟算法进行了研究与分析，并在此基础上设计实现了最佳主时钟算法。
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For every pass, each clock slave component generates and transmits a first timing cell to the clock master.
每一遍，每个从时钟部件产生并发送第一定时信元至主时钟。
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Tstab is equivalent to approximately 512 master clock cycles and depends on the programmed master oscillator frequency.
tstab相当于大约512个主时钟周期，并在程序主振荡器的频率而定。
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SYNCHRONOUS OPERATION For synchronous operation, the same master clock and bit clock should be used for both the transmit and receive directions.
对于同步操作同步操作，相同的主时钟和位时钟都应该用于发送和接收方向。
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Zero- ohm jumper R35 is installed to pass either of these clock sources to the DDX-2000 master clock input.
零欧姆跳线R35小安装通过这些无论对时钟源的DDX - 2000主时钟输入。
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All filter clocks are derived from the 2.048 MHz master clock input, C2i.
所有过滤器时钟来自2.048兆赫主时钟输入，C2i。
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The picture to the right shows the word clock output of the HDSP 9632, which is directly fed from the internal master clock - and with this from SteadyClock.
下图显示了 HDSP 9632 的字时钟输出，它是直接被内部主时钟驱动的，也使用了 SteadyClock 技术。
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A method that initiates several time synchronization passes between clock slave components and a clock master component in a wireless telecommunications system is provided.
一种在无线电信系统内的从时钟部件与主时钟部件之间，启动若干遍时间同步过程的方法。
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Collect and process the time stamp in network drives based on PTP, then synchronize the master and slave clock by using the best master clock algorithm programmed in Java and C language. Allan variance was used to describe properties of the clock.
基于精密时间协议，在网络驱动中对时戳进行采集和处理，采用最佳主时钟算法选取网络主时钟对从时钟进行同步，使用Java语言和C语言混合编程实现软件网络时钟同步，并采用Allan方差公式对时钟性能进行描述。
- 更多网络解释与主时钟相关的网络解释 [注：此内容来源于网络，仅供参考]
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main clock：主时钟
在这里需要区别一个概念:主时钟和主机时钟主时钟(main clock)是指输入主振荡器的时钟主机时钟(mck)指CPU的时钟频率. 主机时钟可以在4个时钟源中选择(时钟选择器)一个作为本身的时钟
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main clock：主时钟,主钟,母钟
main classes 主类 | main clock 主时钟,主钟,母钟 | main closed loop 主闭环
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MCK Main Clock board：主时钟板
MAP Mobile Application Part 移动应用部分 | MCK Main Clock board 主时钟板 | MM Mobility Management 移动性管理
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COM-MCLK-OUT Communication Main Clock Output：串行通信接口主时钟输出
COM Communication 串行通信接口 | COM-MCLK-OUT Communication Main Clock Output 串行通信接口主时钟输出 | COM-MCLK-REQ Communication Main Clock Request 串行通信接口主时钟请求信号
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COM-MCLK-REQ Communication Main Clock Request：串行通信接口主时钟请求信号
COM-MCLK-OUT Communication Main Clock Output 串行通信接口... | COM-MCLK-REQ Communication Main Clock Request 串行通信接口主时钟请求信号 | COM SHUTDOWN Communication Shutdown 串行通信接口关闭,常用于诺基...
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LCD-MCLK Liquid Crystal Display Main Clock：液晶显示器主时钟信号
LCD-MAIN CS Liquid Crystal Display Main Chip Select LCD灯显示片... | LCD-MCLK Liquid Crystal Display Main Clock 液晶显示器主时钟信号 | LCD-MIDI CS Liquid Crystal Display MIDI Chip Select 显示器和弦音片选...
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MCA MasterClock：主时钟
MCU MasterCentralTimingSystem 主中央定时系统 | MCA MasterClock 主时钟 | MCGA MasterClockGenerator 主时钟发生器
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master clock：主时钟
数字音频信号的传送必须叠加上一个采样时钟信号才可以传递,这个采样信号是来自它自身的时钟振荡器,但是这个振荡器必须时刻地和主时钟(Master Clock)进行同步,如果出现了偏差,Dante会自动调节本地时钟的增加或减少以保持与网络基准主时钟同步.
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MC Master Clock：主时钟
MC Media Control 媒体控制 | MC Master Clock 主时钟 | MC Maintenance Center 维护中心
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master clock frequency：主时钟频率
master clock 母钟,主钟 | master clock frequency 主时钟频率 | master clock-pulse generator 主时钟脉冲发生器,母时钟脉冲发生器,母钟脉冲发生器