英语人>词典>英汉 : packed format的中文,翻译,解释,例句
packed format的中文,翻译,解释,例句

packed format

packed format的基本解释
-

压缩格式

更多网络例句与packed format相关的网络例句 [注:此内容来源于网络,仅供参考]

The system is composed of trust model, structure and function design, certificate database design, and implements the core functions of a standard CA system including signing, issuing and revoking certificates. The security communication modular of the system is based on the SSL Protocol to enhance the security of system communications. Besides, the kernel functions of the system are packed into DLL library, including symmetrical encryption algorithms, digest algorithms, digital signature algorithms and certificate operations such as certificate request, certificate building, certificate format conversion etc.

本文的主要工作是:在研究PKI相关技术的基础上,设计了企业CA系统方案,包括信任模型、结构和功能设计、证书库的设计;实现CA系统中最为核心的数字证书管理,提供数字证书的签发、注销和发布等各项功能;实现了基于SSL协议安全通信模块,增强了系统通信的安全性;系统采用动态链接库技术封装了对称加密算法、数字摘要算法、签名算法以及证书处理(包括证书请求、证书生成、证书格式转换等功能),以动态链接库的形式提供调用接口,成为应用的安全基础设施。

The IT Girl's Guide to Blogging With Moxie is packed with the content you need wrapped in casual, engaging dialog and a cheeky, bite-sized format.

资讯科技女童的指南博客moxie是挤得水泄不通的内容您需要包裹在散,搞对话和cheeky ,一口大小的格式。

7 To 3.3 V operating supply voltage 44.1 kHz sampling frequency 16.9344 MHz (384fs) system clock Built-in crystal oscillator circuit 16-bit, MSB rst, rear-packed serial data input format ( 64 fs bit clock) 8-times oversampling digital lter · 32 dB stopband attenuation ·+0.05 to -0.05 dB passband ripple Deemphasis lter operation · 36 dB stopband attenuation ·-0.09 to +0.23 dB deviation from ideal deem- phasis lter characteristics Attenuator · 7-bit attenuator (128 steps) set by microcontrol- ler Soft mute function set by parallel setting ·(approximately 1024/fs total muting time) Mono setting · Left or right channel mono selectable by micro- controller Built-in innity-zero detection circuit , two-channel D/A converter · 3rd-order noise shaper · 32fs oversampling Built-in 3rd-order post-converter low-pass lters 24-pin VSOP package Molybdenum-gate CMOS process

2.7至3.3 V工作电源电压为44.1千赫的采样频率16.9344兆赫(384fs)系统时钟内置晶体振荡器电路的16位,MSB在前,后包装的串行数据输入格式(64飞秒位时钟)8倍超采样数字滤波器·32分贝的阻带衰减·+0.05至-0.05分贝通带纹波去加重滤波器的运作·36 dB抑制频宽衰减·-0.09到0.23 dB的偏差认为不理想,症状困扰评估滤波特性衰减器·7位衰减器(128级)集由单片机在-莱尔软静音功能的平行设置·(共约1024/fs静音时间)单声道设置·左或右声道单声道微控制器可选的内置的无限零检测电路Δ,两通道的D / A转换器·第三阶噪声整形·32fs过采样内置三阶后转换器的低通滤波器24引脚VSOP封装钼栅CMOS工艺

更多网络解释与packed format相关的网络解释 [注:此内容来源于网络,仅供参考]

packed decimal notation:紧缩十进制记法

緊縮十進制鍵 packed decimal key | 緊縮十進制記法 packed decimal notation | 緊縮十進數格式 packed decimal number format

packed decimal number:压缩十进制数

packed decimal format 压缩十进制格式 | packed decimal number 压缩十进制数 | packed format 压缩格式

packed decimal number:组合十进制数

packed decimal 压缩十进制 | packed decimal number 组合十进制数 | packed decimal number format 组合式十进制数格式