地址总线

词组短语

address bus

与地址总线相关的网络例句 [注：此内容来源于网络，仅供参考]

The system bus is divided into three logical functions; the address bus, the data bus and the control bus .

系统总线的功能在逻辑上被划分为三部分：地址总线、数据总线和控制总线。

Memory is by memory address decoder, literacy control circuit, the address bus and the data bus.

存储器是由存储体、地址译码器、读写控制电路、地址总线和数据总线组成。

A memory address consists of binary data being output on an appropriate bus which we call the address bus.

一个存储器地址是由输出到适宜的总线上的二进制数据所组成。这个总线我们称为地址总线。

Address bit 0 of the external address bus when the external data bus is configured for an 8 bit width.

地址位外部地址总线0时的外部数据总线宽度为8位配置。

Contents of a memory location or register within a particular peripheral, ints on the data bus.

设中的存储器地址或寄存器中的内容时，处理器设置地址总线并在数据总线上接收

When the processor wants to read the contents of a memory location or register within a particular peripheral, it sets the address bus

当一个处理器想去写某一特定外设中的存储器地址或寄存器中的内容时，处理器设置地址总线并在数据总线上接收内容。

The circuit comprises a comparison circuit, a negation gate and a first coincidence gate, wherein the comparison circuit is used to output read screen signals of a storage unit corresponding with bus signals of a second port address, the negation gate is used to inverse the read screen signals of the storage unit which are corresponding with the bus signals of the second port address, one input end of the first coincidence gate receives the read screen signals of the storage unit which are corresponding with the bus signals of the second port address after being inversed, the other input end of the first coincidence gate receives the read enable signals of a second port, and the output end of the first coincidence gate is connected with the read enable end of the second port.

所述电路包括：比较电路，用于输出第二端口地址总线信号对应的存储单元读屏蔽信号；非门，用于对第二端口地址总线信号对应的存储单元读屏蔽信号进行非运算；第一与门，第一与门的一路输入端接收非运算后的第二端口地址总线信号对应的存储单元读屏蔽信号，第一与门的另一路输入端接收第二端口的读使能信号，第一与门的输出端连接第二端口的读使能端。

This method reorders the ten least significant bits of offset address according to the value of offset address, and the optimal sorting pattern is transmitted through the high bits of bus without the need for redundant bus lines.

该编码方法根据偏移地址的值域对地址总线的低位进行优化重排，通过高位地址总线传送排序矢量至存储器的地址接收端，相对于传统的地址总线编码方法，具有更低的总线跳变率。

The address is transmitted to the memory through a set of parallel wires called an address bus. A 16-bit address bus can locate 64K(2^16) or 65536 memory locations. A 32-bit address bus can locate 4 Gigas(2^32) of different memory locations.

向存储器传送地址是经过一组为地址总线的并行导线进行的。16位地址总线可以确定64K （2的16次幂）即65536个存储位置。32位地址总线可以确定4G （2的32次幂）个不同的存储位置。

The data location includes memory data memorizer and memory map register, which share uniform data and address buses, at the same time occupy independent physical spaces, respectively, both physical and logic addresses separated and independently addressed, respectively, and can multiplex the same logic address.

内存数据存储器和内存映射寄存器共享统一的数据总线和数据地址总线。同时，内存数据存储器和内存映射寄存器各自占有独立的物理空间，物理地址和逻辑地址均分开，各自独立编址，内存数据存储器和内存映射寄存器对同一逻辑地址可以复用。

与地址总线相关的网络解释 [注：此内容来源于网络，仅供参考]

address bus：地址总线

c、为了降低成本和尽可能减少相互间的干扰信息,要减少总线宽度(Bus width),地址总线(Address Bus)和数据总线(Data Bus)采用多工方式(Multiplex)设计,这样就降低了频宽有效使用率.

address bus：地(位)址汇流道 地址总线

低杂音放大器 低噪音放大器 low noise amplifier | 地(位)址汇流道 地址总线 address bus | 第二级记忆体 二级(辅助)存储器 secondary storage

AB Address Bus：地址总线

1、 地址总线(AB address bus)地址总线(AB)用来由CPU向存储器(ROM)单元和输入/输出接口发送(传输 地址信息的总线. 由于存储器(ROM)单元和输入/输出接口是不向CPU传输信息的,所以地址总线(AB)是单向传输总线.

Address Bus Control：地址总线控制

ABC Absorbing Boundary Condition 吸收边界条件 | Address Bus Control 地址总线控制 | Automatic Bandwidth Control 自动带宽控制

physical address bus：实际地址总线

physical acoustics 物理声学 | physical address bus 实际地址总线 | physical address 物理地址

address bus driver：地址总线驱动器

address buffer 地址缓冲器 | address bus driver 地址总线驱动器 | address calculation 地址计算,地址计算法分类

address bus structure：地址总线结构

地址总线驱动器 address bus driver | 地址总线结构 address bus structure | 地址总线 address bus,AB

Data bus：数据总线

李孝利 韩国RO广告(bus)与 李孝利 韩国RO广告(bus) 不相关的其它视频在计算机系统中 BUS称为总线 是CPU与Memory及I/O间 传输数据或地址信号的线路集合 PC的系统总线有地址总线(address bus) 数据总线(data bus) 控制总线(control bus).

HMA HighwayMemoryAddress：高速公路"存储地址,总线存储地址

HSC HighspeedSelectorChannelunit 高速选择器通道部件 | HMA HighwayMemoryAddress "高速公路"存储地址,总线存储地址 | HNI HighwayNetworkDataandInformation "高速公路"网络数据和信息

SAB SyncAddressBus：同步地址总线

SymmetricalMultipleProcessor 对称多处理器 | SAB SyncAddressBus 同步地址总线 | SBC SyncBurstCache 同步脉冲串高速缓冲存储器